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| 型號： | DS3170+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/230頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX DS3/E3 100-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 640 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | DS3，E3 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 120mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（11x11） |
| 包裝： | 托盤 |
| 包括： | DS3 調(diào)幀器，E3 調(diào)幀器，HDLC 控制器，芯片內(nèi) BERT |
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DS3170 DS3/E3 Single-Chip Transceiver
101 of 230
order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the
highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a
byte in a register and the corresponding byte in a signal.
10.8.4 Transmit Data Storage
The Transmit Data Storage block contains memory for 16 bytes of data and controller circuitry for reading and
writing the memory. The Transmit Data Storage controller functions include filling the memory and maintaining the
memory read and write pointers. The Transmit Data Storage receives data from the microprocessor interface, and
stores the data in memory. The Transmit Trace ID Processor reads the data from the Transmit Data Storage. The
Transmit Data Storage contains the transmit trail trace identifier. Note: The contents of the transmit trail (path) trace
identifier memory will be random data immediately after power-up, and will not change during a reset (
RST or DRST
low).
10.8.5 Transmit Trace ID Processor
The Transmit Trace ID Processor accepts data from Transmit Data Storage, processes the data according to the
Transmit Trace ID mode, and outputs the serial trace ID data stream.
10.8.6 Transmit Trail Trace Processing
The Transmit Trail Trace Processing accepts data from the Transmit Data Storage performs bit reordering and
multiframe alignment insertion.
Bit reordering changes the bit order of each byte. If bit reordering is disabled, the outgoing 8-bit data stream
DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is input from the Transmit Data Storage with the MSB
in TTD[7] and the LSB in TTD[0] of the transmit trace ID data TTD[7:0]. If bit reordering is enabled, the outgoing 8-
bit data stream DT[1:8] is input from the Transmit Data Storage with the MSB is in TTD[0] and the LSB is in TTD[7]
of the transmit trace ID data TTD[7:0]. DT[1] is the first bit transmitted on the outgoing data stream.
Multiframe alignment insertion overwrites the MSB of each trail trace byte with the multiframe alignment signal. The
MSB of the first byte in the trail trace identifier is overwritten with a one, the MSB of the other fifteen bytes in the
trail trace identifier are overwritten with a zero. Multiframe alignment insertion is programmable (on or off).
If transmit data inversion is enabled, the outgoing data is inverted after trail trace processing is performed. Transmit
data inversion is programmable (on or off). If transmit trail trace identifier idle (Idle) is enabled, the trail trace data is
overwritten with all zeros. Transmit Idle is programmable (on or off).
10.8.7 Receive Trace ID Processor
The Receive Trace ID Processor receives the incoming serial trace ID data stream and processes the incoming
data according to the Receive Trace ID mode, and passes the trace ID data on to Receive Data Storage.
The bits in a byte are received MSB first, LSB last. The bits in a byte in an incoming signal are numbered in the
order they are received, 1 (MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the
highest numbered bit (7), and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a
byte in a register and the corresponding byte in a signal.
10.8.8 Receive Trail Trace Processing
The Receive Trail Trace Processing accepts an incoming data line and performs trail trace alignment, trail trace
extraction, expected trail trace comparison, and bit reordering. If receive data inversion is enabled, the incoming
data is inverted before trail trace processing is performed. Receive data inversion is programmable (on or off).
Trail trace alignment determines the trail trace identifier boundary by identifying the multiframe alignment signal.
The multiframe alignment signal (MAS) is located in the MSB of each byte (Figure 10-21). The MAS bits are each
checked for the multiframe alignment start bit, which is a one. Once a multiframe alignment start bit is found, the
remaining fifteen bits of the MAS are verified as being zero. The MAS check is performed one byte at a time.
Multiframe alignment is programmable (on or off). When multiframe alignment is disabled, the incoming bytes are
sequentially stored starting with a random byte.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3170_11 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:DS3/E3 Single-Chip Transceiver Single-Chip Transceiver for DS3 and E3 |
| DS3170+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC DS3/E3 Single-Chip Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3170DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3170 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS3170L | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:DS3/E3 Single-Chip Transceiver |
| DS3170LN | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:DS3/E3 Single-Chip Transceiver |
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