參數(shù)資料
型號: DS3254
英文描述: Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述: 單/雙/三/四路、DS3/E3/STS-1 LIU
文件頁數(shù): 14/71頁
文件大?。?/td> 925K
代理商: DS3254
DS3251/DS3252/DS3253/DS3254
14 of 71
Table 6-G. Transmitter Data Select Options
TDSA
TDSB
E3M
STS
Tx
MODE
Any
DS3
E3
STS-1
DS3
Any
E3
DS3
STS-1
TRANSMIT DATA SELECTED
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
X
0
1
1
0
X
1
0
1
X
0
0
1
1
X
0
X
1
Normal data as input at TPOS and TNEG
Unframed all ones
DS3 AIS per ANSI T1.107 (
Figure 9-2
)
Unframed 100100… pattern
2
- 1 PRBS pattern per ITU O.151
2
15
- 1 PRBS pattern per ITU O.151
Note 1:
This coding of the TDSA, TDSB, E3M, and STS bits allows AIS generation to be enabled by
holding TDSA = 0 and changing TDSB from 0 to 1. The type of DS3 AIS signal is selected by the
STS bit with E3M = 0.
If E3M and/or STS are changed when {TDSA,TDSB} 00, TDSA and TDSB must both be cleared
to 0. After they are cleared, TDSA and TDSB can be configured to transmit a pattern in the new
operating mode.
Note 2:
Table 6-H. Receiver PRBS Pattern Select Options
Rx
MODE
1
0
E3
0
X
DS3
1
1
STS-1
Table 6-I. Hardware Mode Jitter Attenuator Configuration
TJA
RJA
JITTER ATTENUATOR CONFIGURATION
E3M
STS
RECEIVER PRBS PATTERN
SELECTED
2
23
- 1 PRBS pattern per ITU O.151
2
15
- 1 PRBS pattern per ITU O.151
0
0
1
1
0
1
0
1
Disabled
Receive path, 16-bit buffer depth
Transmit path, 16-bit buffer depth
Transmit path, 32-bit buffer depth
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