DS3251/DS3252/DS3253/DS3254
15 of 71
7. REGISTER DESCRIPTIONS
When the DS325x is configured in either of the two CPU bus modes (HW = 0), the registers shown in
Table 7-A
are accessible through the CPU bus interfaces. All registers for the LIU ports are forced to their default values
during an internal power-on reset or when the
RST
pin is driven low. Setting an LIU’s RST bit high forces all
registers for that LIU to their default values. All register bits marked “—” must be written 0 and ignored when read.
The TEST registers must be left at their reset value of 00h for normal operation.
On the DS3253, only registers for LIUs 1, 2, and 3 are available. Writes into LIU 4 address space are ignored.
Reads from LIU 4 address space return all zeros. On the DS3252, address line A5 is not present, limiting the
address space to the LIU 1 and LIU 2 registers. On the DS3251, address lines A5 and A4 are not present, limiting
the address space to the LIU 1 registers.
Table 7-A. Register Map
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
LIU 1
00h
GCR1
E3M
STS
LLB
01h
TCR1
JAL[1]
TBIN
TCINV
02h
RCR1
ITU
RBIN
RCINV
03h
SR1
—
—
TDM
04h
SRL1
JAFL
JAEL
TDML
05h
SRIE1
JAFIE
JAEIE
TDMIE
06h
RCVL1
RCV[7]
RCV[6]
RCV[5]
07h
RCVH1
RCV[15]
RCV[14]
RCV[13]
08h
CACR
T3MOE
E3MOE
STMOE
09h–0Fh
Test Registers
—
—
—
LIU 2
10h
GCR2
E3M
STS
LLB
11h
TCR2
JAL[1]
TBIN
TCINV
12h
RCR2
ITU
RBIN
RCINV
13h
SR2
—
—
TDM
14h
SRL2
JAFL
JAEL
TDML
15h
SRIE2
JAFIE
JAEIE
TDMIE
16h
RCVL2
RCV[7]
RCV[6]
RCV[5]
17h
RCVH2
RCV[15]
RCV[14]
RCV[13]
18h
unused
—
—
—
19h–1Fh
Test Registers
—
—
—
LIU 3
20h
GCR3
E3M
STS
LLB
21h
TCR3
JAL[1]
TBIN
TCINV
22h
RCR3
ITU
RBIN
RCINV
23h
SR3
—
—
TDM
24h
SRL3
JAFL
JAEL
TDML
25h
SRIE3
JAFIE
JAEIE
TDMIE
26h
RCVL3
RCV[7]
RCV[6]
RCV[5]
27h
RCVH3
RCV[15]
RCV[14]
RCV[13]
28h
unused
—
—
—
29h–2Fh
Test Registers
—
—
—
LIU 4
30h
GCR4
E3M
STS
LLB
31h
TCR4
JAL[1]
TBIN
TCINV
32h
RCR4
ITU
RBIN
RCINV
33h
SR4
—
—
TDM
34h
SRL4
JAFL
JAEL
TDML
35h
SRIE4
JAFIE
JAEIE
TDMIE
36h
RCVL4
RCV[7]
RCV[6]
RCV[5]
37h
RCVH4
RCV[15]
RCV[14]
RCV[13]
38h
unused
—
—
—
39h–3Fh
Test Registers
—
—
—
Note 1:
Underlined bits are read-only; all other bits are read-write.
Note 2:
The registers are named REGn, where n = the LIU number (1, 2, 3, or 4). The register names are hyperlinks to the register descriptions.
Note 3:
The bit names are the same for each LIU register set.
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
AMCSEL[1] AMCSEL[0]
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
AMCEN
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
—
RLB
TJA
RJA
PRBS
PRBSL
PRBSIE
RCV[4]
RCV[12]
—
—
TDSA
TPD
RPD
—
PBERL
PBERIE
RCV[3]
RCV[11]
—
—
TDSB
TTS
RTS
—
RCVL
RCVIE
RCV[2]
RCV[10]
—
—
—
RST
JAL[0]
RCVUD
RLOS
RLOSL
RLOSIE
RCV[0]
RCV[8]
—
—
TLBO
RMON
RLOL
RLOLL
RLOLIE
RCV[1]
RCV[9]
—
—