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參數(shù)資料
| 型號： | DS3254 |
| 英文描述： | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| 中文描述： | 單/雙/三/四路、DS3/E3/STS-1 LIU |
| 文件頁數(shù)： | 18/71頁 |
| 文件大?。?/td> | 925K |
| 代理商： | DS3254 |
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DS3251/DS3252/DS3253/DS3254
18 of 71
Register Name:
Register Description:
Register Address:
Bit
Name
Default
Bit 7: ITU CV Mode (ITU).
This bit controls what types of bipolar violations (BPVs) are flagged as code violations
on the RLCV pin and counted in the
RCV
register. It also controls whether or not excessive zero (EXZ) events are
flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth
consecutive zero (E3 mode) in a sequence of zeros.
0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and
counted. EXZ events are also flagged and counted.
1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3
mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not
flagged and counted in any mode.
Bit 6: Receiver Binary Interface Enable (RBIN)
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations.
The B3ZS/HDB3 encoder is enabled.
Bit 5: Receiver Clock Invert (RCINV)
0 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK.
Bit 4: Receiver Jitter Attenuator Enable (RJA).
(Note that
TCR
:TJA = 1 takes precedence over RJA = 1.)
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
Bit 3: Receiver Power-Down Enable (RPD)
0 = enable the receiver
1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated)
Bit 2: Receiver Tri-State Enable (RTS).
This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT,
RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The
RTS
pin is inverted and logically
ORed with this bit.
0 = enable the receiver outputs
1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK)
Bit 1: Receiver Monitor Preamp Enable (RMON)
0 = disable the monitor preamp
1 = enable the monitor preamp
Bit 0: Receive Code-Violation Counter Update (RCVUD).
When this control bit transitions from low to high, the
RCVL
and
RCVH
registers are loaded with the current code-violation count, and the internal code-violation counter
is cleared.
0
1 = Update
RCV
registers and clear internal code-violation counter
RCRn
Receiver Configuration Register
02h, 12h, 22h, 32h
7
6
5
4
3
2
1
0
ITU
0
RBIN
0
RCINV
0
RJA
0
RPD
0
RTS
1
RMON
0
RCVUD
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3254+ | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254A3 | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254A3+ | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254DK | 功能描述:網(wǎng)絡開發(fā)工具 DS3254 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS3254N | 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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