參數(shù)資料
型號： DS3254
英文描述： Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述： 單/雙/三/四路、DS3/E3/STS-1 LIU
文件頁數(shù)： 2/71頁
文件大?。?/td> 925K
代理商： DS3254
DS3251/DS3252/DS3253/DS3254
2 of 71
TABLE OF CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
STANDARDS COMPLIANCE ......................................................................................................... 6
DETAILED DESCRIPTION ............................................................................................................. 7
APPLICATION EXAMPLE .............................................................................................................. 7
BLOCK DIAGRAMS........................................................................................................................ 8
CONTROL INTERFACE MODES.................................................................................................... 9
PIN DESCRIPTIONS..................................................................................................................... 10
REGISTER DESCRIPTIONS......................................................................................................... 15
RECEIVER.................................................................................................................................... 24
8.1
I
NTERFACING TO THE
L
INE
........................................................................................................................... 24
8.2
O
PTIONAL
P
REAMP
..................................................................................................................................... 24
8.3
A
UTOMATIC
G
AIN
C
ONTROL
(AGC)
AND
A
DAPTIVE
E
QUALIZER
..................................................................... 24
8.4
C
LOCK AND
D
ATA
R
ECOVERY
(CDR)........................................................................................................... 24
8.5
L
OSS
-
OF
-S
IGNAL
(LOS) D
ETECTOR
............................................................................................................ 24
8.6
F
RAMER
I
NTERFACE
F
ORMAT AND THE
B3ZS/HDB3 D
ECODER
.................................................................... 25
8.7
R
ECEIVE
L
INE
-C
ODE
V
IOLATION
C
OUNTER
.................................................................................................. 26
8.8
R
ECEIVER
P
OWER
-D
OWN
........................................................................................................................... 26
8.9
R
ECEIVER
J
ITTER
T
OLERANCE
.................................................................................................................... 26
9.
TRANSMITTER............................................................................................................................. 27
9.1
T
RANSMIT
C
LOCK
....................................................................................................................................... 27
9.2
F
RAMER
I
NTERFACE
F
ORMAT AND THE
B3ZS/HDB3 E
NCODER
.................................................................... 27
9.3
P
ATTERN
G
ENERATION
............................................................................................................................... 27
9.4
W
AVESHAPING
, L
INE
B
UILD
-O
UT
, L
INE
D
RIVER
............................................................................................ 28
9.5
I
NTERFACING TO THE
L
INE
........................................................................................................................... 28
9.6
T
RANSMIT
D
RIVER
M
ONITOR
....................................................................................................................... 28
9.7
T
RANSMITTER
P
OWER
-D
OWN
...................................................................................................................... 28
9.8
T
RANSMITTER
J
ITTER
G
ENERATION
(I
NTRINSIC
)........................................................................................... 28
9.9
T
RANSMITTER
J
ITTER
T
RANSFER
................................................................................................................. 28
10.
JITTER ATTENUATOR............................................................................................................. 32
11.
DIAGNOSTICS.......................................................................................................................... 34
11.1
PRBS G
ENERATOR AND
D
ETECTOR
............................................................................................................ 34
11.2
L
OOPBACKS
............................................................................................................................................... 34
12.
CLOCK ADAPTER.................................................................................................................... 35
13.
RESET LOGIC .......................................................................................................................... 35
14.
TRANSFORMERS..................................................................................................................... 36
15.
CPU INTERFACES ................................................................................................................... 37
15.1
P
ARALLEL
I
NTERFACE
................................................................................................................................. 37
15.2
SPI I
NTERFACE
.......................................................................................................................................... 37
16.
JTAG TEST ACCESS PORT AND BOUNDARY SCAN............................................................ 40
16.1
JTAG D
ESCRIPTION
................................................................................................................................... 40
16.2
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
............................................................................. 40
16.3
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
...................................................................................... 42
16.4
JTAG T
EST
R
EGISTERS
.............................................................................................................................. 43
17.
ELECTRICAL CHARACTERISTICS ......................................................................................... 44
18.
PIN ASSIGNMENTS.................................................................................................................. 56
19.
PACKAGE INFORMATION....................................................................................................... 70
20.
THERMAL INFORMATION ....................................................................................................... 71
21.
REVISION HISTORY................................................................................................................. 71
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相關代理商/技術參數(shù)
參數(shù)描述
DS3254+ 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254A3 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254A3+ 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254DK 功能描述:網(wǎng)絡開發(fā)工具 DS3254 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS3254N 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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