參數(shù)資料
型號: DS8007A-EAG+
廠商: Maxim Integrated Products
文件頁數(shù): 4/41頁
文件大小: 0K
描述: IC INTERFACE SMART CARD 48-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 104
應(yīng)用: 智能卡
接口: 并聯(lián)
電源電壓: 2.7 V ~ 6 V
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 管件
安裝類型: 表面貼裝
DS8007A
Multiprotocol Dual Smart Card Interface
12
______________________________________________________________________________________
Pin Description (continued)
PIN
NAME
FUNCTION
21
CPA1
Step-Up Converter Contact 1. Connect a low-ESR capacitor of 220nF between CPA1 and CPA2.
22
CPB1
Step-Up Converter Contact 3. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2.
23
VDDA
Analog Supply Voltage. Positive analog-supply voltage for the step-up converter; can be higher but not
lower than VDD. This pin should be decoupled to AGND with a good quality capacitor.
24
CPB2
Step-Up Converter Contact 4. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2.
25
AGND
Analog Ground
26
CPA2
Step-Up Converter Contact 2. Connect a low-ESR capacitor of 220nF between CPA1 and CPA2.
27
VDD
Digital Supply Voltage. This pin should be decoupled to GND with a good quality capacitor.
28–35
D0–D7
8-Bit Digital I/O. This port functions as the data or address/data communication lines between the host
controller and the DS8007A for the nonmultiplexed and multiplexed operating modes, respectively.
36
RD
Active-Low Parallel Bus Read Strobe Input. In multiplexed mode, this input indicates when the host
processor is reading information from the DS8007A. In nonmultiplexed mode, this pin signals the current
operation is a read (RD = 1) or a write (RD = 0) when CS and WR are low.
37
WR
Active-Low Parallel Bus Write Strobe Input. In multiplexed mode, this input indicates when the host
processor is writing information to the DS8007A. In nonmultiplexed mode, a low on this pin signals the
bus is engaged in a read or write operation.
38
CS
Active-Low Chip-Select Input. This input indicates when the DS8007A is active on the parallel bus.
39
ALE
Address Latch Enable Input. This signal monitors the ALE signal when the host processor bus is
operating in multiplexed mode. Connect this signal to VDD when operating in nonmultiplexed mode.
40
INT
Active-Low Interrupt. This output indicates an interrupt is active.
41
INTAUX
Auxiliary Interrupt Input. This pin serves as an auxiliary interrupt.
42–45
AD3–AD0
Register Selection Address Inputs. These pins function as the address input lines for the nonmultiplexed
configuration and should be connected to ground or VDD in the multiplexed configuration.
46, 47
XTAL2,
XTAL1
Crystal Oscillators. Place a crystal with appropriate load capacitors between these pins if that is the
desired clock source. XTAL1 also acts as an input if there is an external clock source in place of a
crystal.
48
DELAY
External Delay Capacitor Connection. Connect a capacitor from this pin to ground to set the power-on
reset delay.
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