參數(shù)資料
型號: DS80C390
英文描述: Dual CAN High-Speed Microprocessor
中文描述: 雙CAN高速微處理器
文件頁數(shù): 10/58頁
文件大?。?/td> 5486K
代理商: DS80C390
DS80C390
E8h
EAh
EBh
ECh
EDh
EEh
EFh
F0h
F3h
F4h
F5h
F6h
F7h
F8h
FBh
FCh
FDh
FEh
FFh
10 of 58
110199
EIE
MXAX
C1M1C
C1M2C
C1M3C
C1M4C
C1M5C
B
C1M6C
C1M7C
C1M8C
C1M9C
C1M10C
EIP
C1M11C
C1M12C
C1M13C
C1M14C
C1M15C
*Shaded bits are Timed Access protected.
CANBIE
C0IE
C1IE
EWDI
EX5
EX4
EX3
EX2
MSRDY
MSRDY
MSRDY
MSRDY
MSRDY
ETI
ETI
ETI
ETI
ETI
ERI
ERI
ERI
ERI
ERI
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
MTRQ
MTRQ
MTRQ
MTRQ
MTRQ
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
DTUP
DTUP
DTUP
DTUP
DTUP
MSRDY
MSRDY
MSRDY
MSRDY
MSRDY
CANBIP
MSRDY
MSRDY
MSRDY
MSRDY
MSRDY
ETI
ETI
ETI
ETI
ETI
C0IP
ETI
ETI
ETI
ETI
ETI
ERI
ERI
ERI
ERI
ERI
C1IP
ERI
ERI
ERI
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ERI
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
PWDI
INTRQ
INTRQ
INTRQ
INTRQ
INTRQ
EXTRQ
EXTRQ
EXTRQ
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EXTRQ
PX5
EXTRQ
EXTRQ
EXTRQ
EXTRQ
EXTRQ
MTRQ
MTRQ
MTRQ
MTRQ
MTRQ
PX4
MTRQ
MTRQ
MTRQ
MTRQ
MTRQ
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
PX3
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
ROW/TIH
DTUP
DTUP
DTUP
DTUP
DTUP
PX2
DTUP
DTUP
DTUP
DTUP
DTUP
ON-CHIP ARITHMETIC ACCELERATOR
An on-chip math accelerator allows the microcontroller to perform 32- and 16-bit multiplication, division,
shifting, and normalization using dedicated hardware. Math operations are performed by sequentially
loading three special registers. The mathematical operation is determined by the sequence in which three
dedicated SFRs (MA, MB and MC) are accessed, eliminating the need for a special step to choose the
operation. The normalize function facilitates the conversion of 4-byte unsigned binary integers into
floating point format. The following table shows the operations supported by the math accelerator and
their time of execution.
ARITHMETIC ACCELERATOR EXECUTION TIMES
Table 3
Operation
Result
32-bit/16-bit divide
32-bit quotient, 16-bit remainder
16-bit/16-bit divide
16-bit quotient, 16-bit remainder
16-bit/16-bit multiply
32-bit product
32-bit shift left/right
32-bit result
32-bit normalize
32-bit mantissa, 5 bit exponent
Execution Time
36 t
CLCL
24 t
CLCL
24 t
CLCL
36 t
CLCL
36 t
CLCL
The following table demonstrates the procedure to perform mathematical operations using the hardware
math accelerator. The MA and MB registers must be loaded and read in the order shown for proper
operation, although accesses to any other registers can be performed between access to the MA or MB
registers. An access to the MA, MB, or MC registers out of sequence will corrupt the operation, requiring
the software to clear the MST bit to restart the math accelerator state machine. Consult the description of
the MCNT0 SFR for details of how the shift and normalize functions operate.
相關(guān)PDF資料
PDF描述
DS80C390-QNR Dual CAN High-Speed Microprocessor
DS80C390-FCR Dual CAN High-Speed Microprocessor
DS80C390-FNR Dual CAN High-Speed Microprocessor
DS80C390-QCR Dual CAN High-Speed Microprocessor
DS80C410 Network Microcontrollers with Ethernet and CAN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS80C390_00 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:High-Speed Microcontroller User’s Guide Supplement
DS80C390_05 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual CAN High-Speed Microprocessor
DS80C390+FCR 制造商:Maxim Integrated Products 功能描述:MICRO DUAL CAN LQFP PB-FREE - Trays
DS80C390+QCR 制造商:Maxim Integrated Products 功能描述:MICRO DUAL CAN PLCC PB-FREE - Rail/Tube
DS80C390+QNR 制造商:Maxim Integrated Products 功能描述:MICRO DUAL CAN PLCC IND PB-FREE - Rail/Tube