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參數(shù)資料
型號: DS80C400-FNY
廠商: Maxim Integrated Products
文件頁數(shù): 79/97頁
文件大?。?/td> 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
DS80C400 Network Microcontroller
80 of 97
Modification of the CAN registers located in MOVX memory is protected through the SWINT bit. Consult the
description of this bit in the High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement for more
information. The CAN module contains a block of control/status/mask registers, 14 functionally identical message
centers, plus a 15th message center that is receive-only and incorporates a buffered FIFO. Table 20 describes the
organization of the message centers located in MOVX space.
Table 20. CAN Controller MOVX Memory Map
CONTROL/STATUS/MASK REGISTERS
REGISTER
7
6
5
4
3
2
1
0
MOVX DATA
ADDRESS*
C0MID0
MID07
MID06
MID05
MID04
MID03
MID02
MID01
MID00
xxDB00h
C0MA0
M0AA7
M0AA6
M0AA5
M0AA4
M0AA3
M0AA2
M0AA1
M0AA0
xxDB01h
C0MID1
MID17
MID16
MID15
MID14
MID13
MID12
MID11
MID10
xxDB02h
C0MA1
M1AA7
M1AA6
M1AA5
M1AA4
M1AA3
M1AA2
M1AA1
M1AA0
xxDB03h
C0BT0
SJW1
SJW0
BPR5
BPR4
BPR3
BPR2
BPR1
BPR0
xxDB04h
C0BT1
SMP
TSEG26
TSEG25
TSEG24
TSEG13
TSEG12
TSEG11
TSEG10
xxDB05h
C0SGM0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
xxDB06h
C0SGM1
ID20
ID19
ID18
0
xxDB07h
C0EGM0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
xxDB08h
C0EGM1
ID20
ID19
ID18
ID17
ID16
ID15
ID14
ID13
xxDB09h
C0EGM2
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
xxDB0Ah
C0EGM3
ID4
ID3
ID2
ID1
ID0
0
xxDB0Bh
C0M15M0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
xxDB0Ch
C0M15M1
ID20
ID19
ID18
ID17
ID16
ID15
ID14
ID13
xxDB0Dh
C0M15M2
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
xxDB0Eh
C0M15M3
ID4
ID3
ID2
ID1
ID0
0
xxDB0Fh
CAN 0 MESSAGE CENTER 1
RESERVED
xxDB10h–11h
C0M1AR0
CAN 0 MESSAGE 1 ARBITRATION REGISTER 0
xxDB12h
C0M1AR1
CAN 0 MESSAGE 1 ARBITRATION REGISTER 1
xxDB13h
C0M1AR2
CAN 0 MESSAGE 1 ARBITRATION REGISTER 2
xxDB14h
C0M1AR3
CAN 0 MESSAGE 1 ARBITRATION REGISTER 3
WTOE
xxDB15h
C0M1F
DTBYC3
DTBYC2
DTBYC1
DTBYC0
T/R
EX/ST
MEME
MDME
xxDB16h
C0M1D0–7
CAN 0 MESSAGE 1 DATA BYTES 0 to 7
xxDB17h–1Eh
RESERVED
xxDB1Fh
CAN 0 MESSAGE CENTERS 2 to 14
MESSAGE CENTER 2 REGISTERS (similar to Message Center 1)
xxDB20h–2Fh
MESSAGE CENTER 3 REGISTERS (similar to Message Center 1)
xxDB30h–3Fh
MESSAGE CENTER 4 REGISTERS (similar to Message Center 1)
xxDB40h–4Fh
MESSAGE CENTER 5 REGISTERS (similar to Message Center 1)
xxDB50h–5Fh
MESSAGE CENTER 6 REGISTERS (similar to Message Center 1)
xxDB60h–6Fh
MESSAGE CENTER 7 REGISTERS (similar to Message Center 1)
xxDB70h–7Fh
MESSAGE CENTER 8 REGISTERS (similar to Message Center 1)
xxDB80h–8Fh
MESSAGE CENTER 9 REGISTERS (similar to Message Center 1)
xxDB90h–9Fh
MESSAGE CENTER 10 REGISTERS (similar to Message Center 1)
xxDBA0h–AFh
MESSAGE CENTER 11 REGISTERS (similar to Message Center 1)
xxDBB0h–BFh
MESSAGE CENTER 12 REGISTERS (similar to Message Center 1)
xxDBC0h–CFh
MESSAGE CENTER 13 REGISTERS (similar to Message Center 1)
xxDBD0h–DFh
MESSAGE CENTER 14 REGISTERS (similar to Message Center 1)
xxDBE0h–EFh
CAN 0 MESSAGE CENTER 15
Reserved
xxDBF0h–F1h
C0M15AR0
CAN 0 MESSAGE 15 ARBITRATION REGISTER 0
xxDBF2h
C0M15AR1
CAN 0 MESSAGE 15 ARBITRATION REGISTER 1
xxDBF3h
C0M15AR2
CAN 0 MESSAGE 15 ARBITRATION REGISTER 2
xxDBF4h
C0M15AR3
CAN 0 MESSAGE 15 ARBITRATION REGISTER 3
WTOE
xxDBF5h
C0M15F
DTBYC3
DTBYC2
DTBYC1
DTBYC0
0
EX/ST
MEME
MDME
xxDBF6h
C0M15D0—
C0M15D7
CAN 0 MESSAGE 15 DATA BYTE 0 to 7
xxDBF7h–FEh
Reserved
xxDBFFh
*The first byte of the CAN 0 MOVX memory address is dependent on the setting of the CMA bit (MCON.5) CMA = 0, xx = 00; CMA = 1, xx = FF.
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