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參數資料
| 型號： | DS80C400-FNY |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 82/97頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 75MHZ 16MB HP 100-LQFP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS |
| 產品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標準包裝： | 90 |
| 系列： | 80C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 75MHz |
| 連通性： | 1 線，CAN，EBI/EMI，以太網，SIO，UART/USART |
| 外圍設備： | 電源故障復位，WDT |
| 輸入/輸出數： | 64 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.62 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
| 配用： | DS80C400-KIT#-ND - EVAL KIT FOR DS80C400 |
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DS80C400 Network Microcontroller
83 of 97
Error Counter Interrupt Generation
The CAN module can be configured to alert the microcontroller when either 96 or 128 errors have been detected by
the transmit or receive error counters. The error-count select bit, ERCS (C0C.1), selects whether the limit is 96
(ERCS = 0) or 128 (ERCS = 1) errors. When the error limit is exceeded, the CAN error-count exceeded bit CECE
(C0S.6) is set. If the ERIE, C0IE, and EA SFR bits are configured, an interrupt is generated. If the ERCS bit is set,
the device generates an interrupt when the CECE bit is set or cleared, if the interrupt is enabled.
Bit Timing
Bit timing of the CAN transmission can be adjusted per the CAN 2.0B specification. The CAN 0 bus timing register
zero (C0BT0), located in the control/status/mask register block in MOVX memory, controls the PHASE_SEG1 and
PHASE_SEG2 time segments and the baud rate prescaler (BPR5–BPR0). The CAN 0 bus timing register one
(C0BT1) contains the controls for the sampling rate and the number of clock cycles assigned to the Phase
Segment 1 and 2 portions of the nominal bit time. The values of both of the bus timing registers are automatically
loaded into the CAN controller following each software change of the SWINT bit from a 1 to a 0 by the
microcontroller. The bit timing parameters must be set before starting operation of the CAN controller. These
registers are modifiable only during a software initialization, (SWINT = 1), when the CAN controller is not in a bus-
off mode, and after the removal of a system reset or a CAN reset. To avoid unpredictable behavior of the CAN
controller, the software cannot clear the SWINT bit when TSEG1 and TSEG2 are both cleared to 0.
1-Wire Bus Master
The DS80C400 incorporates a 1-Wire bus master to support communication to external 1-Wire devices. The bus
master provides complete control of the 1-Wire bus and coordinates transmit (Tx)/receive (Rx) activities with
minimal supervision by the CPU. All timing and control sequences for the bus are generated within the bus master.
Communication between the CPU and the bus master is accomplished through read/write access of the 1-Wire
master address (OWMAD; EEh) and 1-Wire master data (OWMDR; EFh) SFRs. When 1-Wire bus activity
generates a condition that requires servicing by the CPU, the bus master sets the appropriate status bit to create
an interrupt request to the CPU. If the 1-Wire bus master interrupt source has been enabled, the CPU services the
request according to the priority that has been assigned. The 1-Wire bus master supports bit banging, search ROM
accelerator, and overdrive modes. Detailed operation of the 1-Wire bus is described in The Book of iButton
Standards (www.maxim-ic.com/iButtonBook).
Communicating with the Bus Master
The microcontroller interface to the 1-Wire bus master is through two SFRs, 1-Wire master address (OWMAD;
EEh), and 1-Wire master data (OWMDR; EFh). These two registers allow read/write access of the six internal
registers of the 1-Wire bus master. The internal registers provide a means for the CPU to configure and control
transmit/receive activity through the bus master.
The three least significant bits (A2:A0) of the OWMAD SFR specify the address of the internal register to be
accessed. The OWMDR SFR is used for read/write access to the implemented bits of the specified internal
register. All internal registers are read/write accessible except the interrupt flag register (xxxxx010b), which allows
only read access to interrupt status flags. It should also be noted that all writes to the Tx/Rx buffer register
(xxxxx001b) are directed to the Tx buffer and all reads retrieve data from the Rx buffer. The 1-Wire bus master
internal register map is shown in Table 22.
Table 22. 1-Wire Bus Master Internal Register Map
REGISTER ADDRESS*/
FUNCTION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
000
Command
—
OW_IN
FOW
SRA
1WR
001
Tx/Rx Buffer
D7
D6
D5
D4
D3
D2
D1
D0
010
Interrupt Flag
OW_LOW
OW_SHORT
RSRF
RBF
TEMT
TBE
PDR
PD
011
Interrupt Enable
EOWL
EOWSH
ERSF
ERBF
ETMT
ETBE
—
EPD
100
Clock Divisor
CLK_EN
—
DIV2
DIV1
DIV0
PRE1 PRE0
101
Control
EOWMI
OD
BIT_CTL
STP_SPLY
STPEN
EN_FOW
PPM
LLM
*Logic states represented by A2:A0 other than those listed in the table are considered to be invalid addresses and are not supported by the bus
master. When OWMAD contains an invalid address, reads of OWMDR return invalid data, and writes to OWMDR do not change the internal
register contents.
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| DS80C400-FNY+ | 功能描述:8位微控制器 -MCU Network MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| DS80C400-KIT | 功能描述:EVAL KIT FOR DS80C400 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:- 產品培訓模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產品:Blackfin? BF50x Series Processors 標準包裝:1 系列:Blackfin® 類型:DSP 適用于相關產品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關產品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| DS80C400-KIT# | 功能描述:開發(fā)板和工具包 - 8051 RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
| DS80C410 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
| DS80C410_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Network Microcontrollers with Ethernet and CAN |
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