
Data Sheet
March 2000
DSP1629 Digital Signal Processor
102
Lucent Technologies Inc.
11 Timing Characteristics for 2.7 V Operation
(continued)
11.3 Reset Synchronization
*
See Table 62 for input clock electrical requirements.
Notes:
CKO
1
and CKO
2
are two possible CKO states before reset. CKO is free-running.
If the rising edge of RSTB (low to high) is captured instead by the falling edge of CKO (high to low), CKO and CKI will be in-phase at t5 + 2 x t6.
Figure 38. Reset Synchronization Timing
Table 110. Timing Requirements for Reset Synchronization Timing
Abbreviated Reference
t126
Parameter
Min
3
Max
T/2 – 1
Unit
ns
Reset Setup (high to high)
5-4011 (F).a
CKI
*
V
IH
V
IL
t126
t5 + 2 x t6
RSTB
V
IH
V
IL
V
IH
V
IL
CKO
V
IH
V
IL
CKO