Data Sheet
March 2000
DSP1629 Digital Signal Processor
54
Lucent Technologies Inc.
5 Software Architecture
(continued)
Table 38. ioc Register
*
Bit
15
Field
RSVD
EXTROM CKO2
* The field definitions for the
ioc
register are different from the DSP1610.
14
13
12
11
10
9
8—7
CKO[1:0]
6—4
RSVD
3—0
EBIOH
WEROM
ESIO2
SIOLBC
DENB[3:0]
ioc Fields
ioc Field
EXTROM
CKO2
EBIOH
WEROM
ESIO2
SIOLBC
CKO[1:0]
DENB3
DENB2
DENB1
DENB0
Description
If 1, sets AB15 low during external memory accesses when WEROM = 1.
CKO configuration (see below).
If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins.
If 1, allows writing into external program (X) memory.
If 1, enables SIO2 and low half of BIO, and disables PHIF from pins.
If 1, DO1 and DO2 looped back to DI1 and DI2.
CKO configuration (see below).
If 1, delay EROM.
If 1, delay ERAMHI.
If 1, delay IO.
If 1, delay ERAMLO.
CKO2
—
0
0
CKO1
—
0
0
CKO0
—
0
1
CKO Output
Description
—
Free-running clock.
*
,
Wait-stated clock.
*
,
,
Held high.
Held low.
Output of CKI buffer.
Sequenced, wait-stated clock.*,
,
,
**
1X
CKI
PLL
CKI x M/(2N)
CKI x (M/(2N)) / [1 + W]
* The phase of CKI is synchronized by the rising edge of RSTB.
When SLOWCKI is enabled in the
powerc
register, these options reflect the low-speed internal ring oscillator.
The wait-stated clock reflects the internal instruction cycle and may be stretched based on the
mwait
register setting (see Table 36). During
sequenced external memory accesses, it completes one cycle.
**The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based on the
mwait
register setting (see Table 36).
CKI/(1 + W)
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
CKI
CKI
CKI/(1 + W)
CKI x (M/(2N)) / [1 + W]
Reserved
Reserved