參數(shù)資料
型號: DSP1629
英文描述: TVS 400W 64V UNIDIRECT SMA
中文描述: DSP1629數(shù)字信號處理器
文件頁數(shù): 77/126頁
文件大小: 1993K
代理商: DSP1629
Data Sheet
March 2000
DSP1629 Digital Signal Processor
Lucent Technologies Inc.
77
10 Timing Characteristics for 3.0 V Operation
(continued)
10.1 DSP Clock Generation
*
Free-running clock.
Wait-stated clock (see Table 38).
§ W = number of wait-states.
See Table 62 for input clock electrical requirements.
Figure 12. I/O Clock Timing Diagram
Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.
Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
T = internal clock period, set by CKI or by CKI and the PLL parameters.
Table 66. Timing Requirements for Input Clock
Abbreviated Reference
t1
t2
t3
Parameter
Min
20
10
10
Max
Unit
ns
ns
ns
Clock In Period (high to high)
Clock In Low Time (low to high)
Clock In High Time (high to low)
Table 67. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference
t4
t5
t6
t6a
Parameter
Min
T
0.74
Max
10
10
3.8
Unit
ns
ns
ns
μ
s
Clock Out High Delay
Clock Out Low Delay (high to low)
Clock Out Period (low to low)
Clock Out Period with SLOWCKI Bit Set in powerc
Register (low to low)
5-4009 (F).a
t4
t1
t2
1X CKI*
t5
CKO
t3
t6, t6a
CKO
EXTERNAL MEMORY CYCLE
W = 1
§
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