GNDN
參數(shù)資料
型號： DSP56301VF100
廠商： Freescale Semiconductor
文件頁數(shù)： 114/124頁
文件大?。?/td> 0K
描述： IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告： DSP56301 Discontinuation 12/Nov/2009
標準包裝： 60
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 252-BGA
供應商設(shè)備封裝： 252-MAPBGA（21x21）
包裝： 托盤
Clock
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-5
1.3 Clock
1.4 Phase Lock Loop (PLL)
GNDN
Bus Control Ground
Isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GNDH
Host Ground
Isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other chip ground connections.
The user must provide adequate external decoupling capacitors.
GNDS
ESSI, SCI, and Timer Ground
Isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all GND inputs except GNDP and GNDP1 to each other
internally. On those packages, all ground connections except GNDP and GNDP1 are labeled GND.
Table 1-4.
Clock Signals
Signal Name
Type
State During
Reset
Signal Description
EXTAL
Input
External Clock/Crystal Input
Interfaces the internal crystal oscillator input to an external crystal or an
external clock.
XTAL
Output
Chip-driven
Crystal Output
Connects the internal crystal oscillator output to an external crystal. If an
external clock is used, leave XTAL unconnected.
Table 1-5.
Phase Lock Loop Signals
Signal Name
Type
State During
Reset
Signal Description
CLKOUT
Output
Chip-driven
Clock Output
Provides an output clock synchronized to the internal core clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
PCAP
Input
PLL Capacitor
Connects an off-chip capacitor to the PLL filter. Connect one capacitor
terminal to PCAP and the other terminal to VCCP.
If the PLL is not used, PCAP can be tied to VCC, GND, or left floating.
Table 1-3.
Grounds
Ground Name
Description
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