參數(shù)資料
型號(hào): DSP56301VF100
廠商: Freescale Semiconductor
文件頁數(shù): 62/124頁
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告: DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝: 60
系列: DSP563xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 100MHz
非易失內(nèi)存: ROM(9 kB)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 252-BGA
供應(yīng)商設(shè)備封裝: 252-MAPBGA(21x21)
包裝: 托盤
DSP56301 Technical Data, Rev. 10
2-16
Freescale Semiconductor
Specifications
2.5.5.2 DRAM Timing
The selection guides in Figure 2-14 and Figure 2-17 are for primary selection only. Final selection should be based
on the timing in the following tables. For example, the selection guide suggests that four wait states must be used
for 100 MHz operation in Page Mode DRAM. However, using the information in the appropriate table, a designer
could choose to evaluate whether fewer wait states might be used by determining which timing prevents operation
at 100 MHz, by running the chip at a slightly lower frequency (for example, 95 MHz), by using faster DRAM (if it
becomes available), and by manipulating control factors such as capacitive and resistive load to improve overall
system performance.
Figure 2-14.
DRAM Page Mode Wait States Selection Guide
Chip frequency
(MHz)
DRAM type
(tRAC ns)
100
80
70
60
40
66
80
100
1 Wait state
2 Wait states
3 Wait states
4 Wait states
Note:
This figure should be used for primary selection. For exact
and detailed timings see the following tables.
50
120
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