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參數(shù)資料
型號(hào)： DSP56303AG100
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 25/108頁(yè)
文件大小： 0K
描述： IC DSP 24BIT 100MHZ 144-LQFP
特色產(chǎn)品： DSP56303 24-bit Digital Signal Processor
標(biāo)準(zhǔn)包裝： 60
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-3
2.5 AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.3 V
and a VIH minimum of 2.4 V for all pins except EXTAL, which is tested using the input levels shown in Note 6 of
the previous table. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50 percent point of the respective input signal transition. DSP56303 output levels are
measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively.
Note:
Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15
MHz and rated speed.
2.5.1
Internal Clocks
Notes:
1.
Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
2.
Section 4.3 provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these
results, all inputs must be terminated (that is, not allowed to float). Measurements are based on synthetic intensive DSP
benchmarks (see Appendix A). The power consumption numbers in this specification are 90 percent of the measured results
of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCC = 3.3 V at TJ =
100°C.
3.
In order to obtain these results, all inputs must be terminated (that is, not allowed to float).
4.
In order to obtain these results, all inputs that are not disconnected at Stop mode must be terminated (that is, not allowed to
float). PLL and XTAL signals are disabled during Stop state.
5.
Periodically sampled and not 100 percent tested.
6.
VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF
7.
This characteristic does not apply to XTAL and PCAP.
8.
Driving EXTAL to the low VIHX or the high VILX value may cause additional power consumption (DC current). To minimize
power consumption, the minimum VIHX should be no lower than
0.9
× V
CC and the maximum VILX should be no higher than 0.1 × VCC.
Table 2-4.
Internal Clocks, CLKOUT
Characteristics
Symbol
Expression1, 2
Min
Typ
Max
Internal operation frequency and CLKOUT
with PLL enabled
f—
(Ef
× MF)/
(PDF
× DF)
—
Internal operation frequency and CLKOUT
with PLL disabled
f—
Ef/2
—
Internal clock and CLKOUT high period
With PLL disabled
With PLL enabled and MF
≤4
With PLL enabled and MF > 4
TH
—
0.49
× ETC ×
PDF
× DF/MF
0.47
× ETC ×
PDF
× DF/MF
ETC
—
0.51
× ETC ×
PDF
× DF/MF
0.53
× ETC ×
PDF
× DF/MF
Internal clock and CLKOUT low period
With PLL disabled
With PLL enabled and MF
≤4
With PLL enabled and MF > 4
TL
—
0.49
× ETC ×
PDF
× DF/MF
0.47
× ETC ×
PDF
× DF/MF
ETC
—
0.51
× ETC ×
PDF
× DF/MF
0.53
× ETC ×
PDF
× DF/MF
Internal clock and CLKOUT cycle time with
PLL enabled
TC
—ETC × PDF ×
DF/MF
—
Table 2-3.
DC Electrical Characteristics6 (Continued)
Characteristics
Symbol
Min
Typ
Max
Unit
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