t
參數(shù)資料
型號: DSP56303AG100
廠商: Freescale Semiconductor
文件頁數(shù): 44/108頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 100MHZ 144-LQFP
特色產(chǎn)品: DSP56303 24-bit Digital Signal Processor
標(biāo)準(zhǔn)包裝: 60
系列: DSP563xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時鐘速率: 100MHz
非易失內(nèi)存: ROM(576 B)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
DSP56303 Technical Data, Rev. 11
2-20
Freescale Semiconductor
Specifications
172
RAS assertion to row address not valid
tRAH
1.75
× TC 4.0
13.5
ns
173
Column address valid to CAS assertion
tASC
0.75
× T
C 4.0
3.5
ns
174
CAS assertion to column address not valid
tCAH
5.25
× TC 4.0
48.5
ns
175
RAS assertion to column address not valid
tAR
7.75
× TC 4.0
73.5
ns
176
Column address valid to RAS deassertion
tRAL
6
× T
C 4.0
56.0
ns
177
WR deassertion to CAS assertion
tRCS
3.0
× TC 4.0
26.0
ns
178
CAS deassertion to WR
4 assertion
tRCH
1.75
× TC – 3.7
13.8
ns
179
RAS deassertion to WR4 assertion
tRRH
0.25
× T
C 2.0
0.5
ns
180
CAS assertion to WR deassertion
tWCH
5
× TC 4.2
45.8
ns
181
RAS assertion to WR deassertion
tWCR
7.5
× TC 4.2
70.8
ns
182
WR assertion pulse width
tWP
11.5
× T
C 4.5
110.5
ns
183
WR assertion to RAS deassertion
tRWL
11.75
× TC 4.3
113.2
ns
184
WR assertion to CAS deassertion
tCWL
10.25
× TC 4.3
98.2
ns
185
Data valid to CAS assertion (write)
tDS
5.75
× T
C 4.0
53.5
ns
186
CAS assertion to data not valid (write)
tDH
5.25
× TC 4.0
48.5
ns
187
RAS assertion to data not valid (write)
tDHR
7.75
× TC 4.0
73.5
ns
188
WR assertion to CAS assertion
tWCS
6.5
× T
C 4.3
60.7
ns
189
CAS assertion to RAS assertion (refresh)
tCSR
1.5
× TC 4.0
11.0
ns
190
RAS deassertion to CAS assertion (refresh)
tRPC
2.75
× TC 4.0
23.5
ns
191
RD assertion to RAS deassertion
tROH
11.5
× T
C 4.0
111.0
ns
192
RD assertion to data valid
tGA
10
× TC 7.0
93.0
ns
193
RD deassertion to data not valid
5
tGZ
0.0
ns
194
WR assertion to data active
0.75
× T
C – 1.5
6.0
ns
195
WR deassertion to data high impedance
0.25
× TC
—2.5
ns
Notes:
1.
The number of wait states for an out-of-page access is specified in the DRAM Control Register.
2.
The refresh period is specified in the DRAM Control Register.
3.
Use the expression to compute the maximum or minimum value listed (or both if the expression includes
±) .
4.
Either tRCH or tRRH must be satisfied for read cycles.
5.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Table 2-11.
DRAM Out-of-Page and Refresh Timings, Eleven Wait States1,2 (Continued)
No.
Characteristics
Symbol
Expression3
100 MHz
Unit
Min
Max
相關(guān)PDF資料
PDF描述
V300A3V3E264BL3 CONVERTER MOD DC/DC 3.3V 264W
KRM55WR72A156MH01K CAP CER 15UF 100V 20% X7R 2220
VI-B51-CY-F2 CONVERTER MOD DC/DC 12V 50W
MLP2012S4R7M INDUCTOR MULTILAYER 4.7UH 0805
DSPB56374AE IC DSP 24BIT 150MHZ 52-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56303AG100B1 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56303AG100R2 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56303EVM 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP56303 Eval Kit RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56303EVMCL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56303EVM DSP56303EVM Kit Contents List
DSP56303EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56303 EVM Users Manual