參數(shù)資料
型號(hào)： DSP56303AG100
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 56/108頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 100MHZ 144-LQFP
特色產(chǎn)品： DSP56303 24-bit Digital Signal Processor
標(biāo)準(zhǔn)包裝： 60
系列： DSP563xx
類(lèi)型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤(pán)
AC Electrical Characteristics
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
2-31
340
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=0)4, 7, 8
—19.3
ns
341
Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=1, open drain host request)
4, 7, 8, 9
—300.0
ns
Notes:
1.
See the Programmer’s Model section in the chapter on the HI08 in the
DSP56303 User’s Manual.
2.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3.
This timing is applicable only if two consecutive reads from one of these registers are executed.
4.
The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the
Single Data Strobe mode.
5.
The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
6.
The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
7.
The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.
8.
The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the
Little Endian mode (HLEND = 1).
9.
In this calculation, the host request signal is pulled up by a 4.7 k
resistor in the Open-drain mode.
10. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF
11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.
12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3
× Tc).
Figure 2-27.
Host Interrupt Vector Register (IVR) Read Timing Diagram
Table 2-16.
Host Interface Timings1,2,12 (Continued)
No.
Characteristic10
Expression
100 MHz
Unit
Min
Max
HACK
H[0–7]
HREQ
329
317
318
328
326
327
Note: The IVR is read only by an MC680xx host processor in non-multiplexed mode.
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