參數(shù)資料
型號： DSP56366UM
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號處理器
文件頁數(shù)： 32/110頁
文件大?。?/td> 1273K
代理商： DSP56366UM
DSP56366 Technical Data, Rev. 3.1
3-6
Freescale Semiconductor
3.8
Phase Lock Loop (PLL) Characteristics
3.9
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
1
4
EXTAL cycle time
2
With PLL disabled
With PLL enabled
ET
C
8.33 ns
8.33 ns
∞
273.1
μ
s
7
Instruction cycle time = I
CYC
= T
C4, 2
With PLL disabled
With PLL enabled
I
CYC
16.66 ns
8.33 ns
∞
8.53
μ
s
1
Measured at 50% of the input transition.
2
The maximum value for PLL enabled is given for minimum V
CO
and maximum MF.
3
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
4
The maximum value for PLL enabled is given for minimum VCO and maximum DF.
Table 3-6 PLL Characteristics
Characteristics
Min
Max
Unit
V
CO
frequency when PLL enabled (MF
×
E
f
×
2/PDF)
30
240
MHz
PLL external capacitor (PCAP pin to V
CCP
) (C
PCAP
)
1
@ MF
≤
4
@ MF > 4
1
C
PCAP
is the value of the PLL capacitor (connected between the PCAP pin and V
CCP
). The recommended value in pF
for C
PCAP
can be computed from one of the following equations:
(MF x 680)-120
, for MF
≤
4
or
MF x 1100
, for MF > 4.
(MF
×
580)
100
MF
×
830
(MF
×
780)
140
MF
×
1470
pF
No.
Characteristics
Expression
Min
Max
Unit
8
Delay from RESET assertion to all pins at reset value
2
—
—
26.0
ns
9
Required RESET duration
3
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
During normal operation
50
×
ET
C
1000
×
ET
C
2.5
×
T
C
416.7
8.3
20.8
—
—
—
ns
μ
s
ns
10
Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)
4
Minimum
Maximum
3.25
×
T
C
+ 2.0
20.25 T
C
+ 7.50
29.1
—
—
176.2
ns
ns
13
Mode select setup time
30.0
—
ns
Table 3-5 Clock Operation (continued)
No.
Characteristics
Symbol
Min
Max
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
DSP56371AF180 制造商:Freescale Semiconductor 功能描述:
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