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參數(shù)資料
| 型號： | DSP56366UM |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 33/110頁 |
| 文件大?。?/td> | 1273K |
| 代理商： | DSP56366UM |
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DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor
3-7
14
Mode select hold time
0.0
—
ns
15
Minimum edge-triggered interrupt request assertion width
5.5
—
ns
16
Minimum edge-triggered interrupt request deassertion width
5.5
—
ns
17
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
4.25
×
T
C
+ 2.0
7.25
×
T
C
+ 2.0
37.4
62.4
—
—
ns
ns
18
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution
10
×
T
C
+ 5.0
88.3
—
ns
19
Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts
5
3.75
×
T
C
+ WS
×
T
C
– 10.94
—
Note
6
ns
20
Delay from RD assertion to interrupt request deassertion for
level sensitive fast interrupts
5
3.25
×
T
C
+ WS
×
T
C
– 10.94
—
Note 6
ns
21
Delay from WR assertion to interrupt request deassertion for
level sensitive fast interrupts
5
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS
≥
4
(WS + 3.5)
×
T
C
– 10.94
(WS + 3.5)
×
T
C
– 10.94
(WS + 3)
×
T
C
– 10.94
(WS + 2.5)
×
T
C
– 10.94
—
—
—
—
Note 6
Note 6
Note 6
Note 6
ns
24
Duration for IRQA assertion to recover from Stop state
4.9
—
25
Delay from IRQA assertion to fetch of first instruction (when
exiting Stop)
2, 7
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (OMR Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No
Stop Delay)
PLC
×
ET
C
×
PDF + (128 K
PLC/2)
×
T
C
PLC
×
ET
C
×
PDF + (23.75
±
0.5)
×
T
C
(8.25
±
0.5)
×
T
C
—
—
64.6
—
—
72.9
ms
ms
ms
26
Duration of level sensitive IRQA assertion to ensure interrupt
service (when exiting Stop)
2, 7
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is enabled (OMR Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop
delay is not enabled (OMR Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (implies no
Stop delay)
PLC
×
ET
C
×
PDF + (128K
PLC/2)
×
T
C
PLC
×
ET
C
×
PDF + (20.5
±
0.5)
×
T
C
5.5
×
T
C
—
—
45.8
—
—
—
ms
ms
ns
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
1
(continued)
No.
Characteristics
Expression
Min
Max
Unit
相關PDF資料 |
PDF描述 |
|---|---|
| DSP56367P | 24-Bit Audio Digital Signal Processor |
| DSP56367UM | 24-Bit Audio Digital Signal Processor |
| DSP56600 | Implementing Viterbi Decoders Using the VSL Instruction on DSP Families |
| DSP56852E | 16-bit Digital Signal Controllers |
| DSP56852VFE | 16-bit Digital Signal Controllers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56367 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| DSP56367P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56367UM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56371 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device |
| DSP56371AF180 | 制造商:Freescale Semiconductor 功能描述: |
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