參數(shù)資料
型號(hào)： DSP56852VFE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 21/48頁(yè)
文件大?。?/td> 731K
代理商： DSP56852VFE
External Clock Operation
56852 Technical Data, Rev. 8
Freescale Semiconductor
21
Figure 4-5
shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached V
OL
or V
OH
Data Invalid state, when a signal level is in transition between V
OL
and V
OH
Figure 4-5 Signal States
4.5 External Clock Operation
The 56852 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
4.5.1
Crystal Oscillator for Use with PLL
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in
Table 4-6
.
In
Figure 4-6
a typical crystal oscillator circuit is
shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Figure 4-6 Crystal Oscillator
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
Data Active
Sample External Crystal
Parameters:
R
z
= 10M
Ω
TOD_SEL bit in CGM may be set to
0 or 1. 0 is recommended.
Crystal Frequency = 2–4MHz (optimized for 4MHz)
EXTAL XTAL
R
z
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