參數(shù)資料
型號(hào): DSP56852VFE
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 3/48頁(yè)
文件大?。?/td> 731K
代理商: DSP56852VFE
56852 Technical Data, Rev. 8
Freescale Semiconductor
3
56852 Block Diagram
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
PLL
Clock
Generator
16-Bit
56800E Core
XTAL
EXTAL
Interrupt
Controller
COP/
Watch-
dog
1 Quad
Timer
or A17,
A18
2
CLKO
muxed
(
A20
)
External Bus
Interface Unit
6
RESET
IRQA
IRQB
V
DD
V
SSIO
V
DDA
V
SSA
WR Enable
RD Enable
CS[2:0] muxed (GPIOA)
A0-16
D0-D12[12:0]
6
Program Memory
6144 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
4096 x 16 SRAM
PDB
PDB
CDBR
CDBW
XAB1
XAB2
XDB2
GPIOC
SCI or
GPIOE
IPBus Bridge (IPBB)
3
muxed (D13-15)
3
6
A17-18 muxed (timer pins)
A19 muxed (CS3)
D13-15 muxed (Mode A,B,C)
V
DDIO
6
Integration
Module
System
P
O
R
O
S
C
Decoding
Peripherals
Peripheral
Address
Decoder
Peripheral
Device
Selects
System
Address
Decoder
RW
Control
IPAB
IPWDB
IPRDB
2
System
Device
System
Bus
Control
R/W Control
Memory
PAB
PAB
CDBR
CDBW
Clock
resets
V
SS
3
SSI or
SPI or
External Data
Bus Switch
Bus Control
External Address
Bus Switch
DSP56852 General Description
120 MIPS at 120MHz
6K x 16-bit Program SRAM
4K x 16-bit Data SRAM
1K x 16-bit Boot ROM
21 External Memory Address lines, 16 data lines and
four chip selects
One (1) Serial Port Interface (SPI) or one (1) Improved
Synchronous Serial Interface (ISSI)
One (1) Serial Communication Interface (SCI)
Interrupt Controller
General Purpose 16-bit Quad Timer
JTAG/Enhanced On-Chip Emulation (OnCE) for
unobtrusive, real-time debugging
Computer Operating Properly (COP)/Watchdog Timer
81-pin MAPBGA package
Up to 11 GPIO
相關(guān)PDF資料
PDF描述
DSP56853E 16-bit Digital Signal Controllers
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