參數(shù)資料
型號(hào)： DSP56858VF120
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁數(shù)： 27/64頁
文件大?。?/td> 956K
代理商： DSP56858VF120
AC Electrical Characteristics
56858 Technical Data, Rev. 6
Freescale Semiconductor
27
V
DD
should not be allowed to rise early (1). This is usually avoided by running the regulator for the V
DD
supply (1.8V) from the voltage generated by the 3.3V V
DDIO
supply, see
Figure 4-3
. This keeps V
DD
from
rising faster than V
DDIO
.
V
DD
should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in
Figure 4-3
. The series diodes forward bias when the difference between V
DDIO
and V
DD
reaches
approximately 2.1, causing V
DD
to rise as V
DDIO
ramps up. When the V
DD
regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
V
DDIO
> V
DD
> (V
DDIO
- 2.1V)
In practice, V
DDA
is typically connected directly to V
DDIO
with some filtering.
Figure 4-3 Example Circuit to Control Supply Sequencing
4.4 AC Electrical Characteristics
Timing waveforms in
Section 4.3
are tested with a V
IL
maximum of 0.8V and a V
IH
minimum of 2.0V for
all pins except XTAL, which is tested using the input levels in
Section 4.2
.
In
Figure 4-4
the levels of V
IH
and V
IL
for an input signal are shown.
Figure 4-4 Input Signal Measurement References
3.3V
Regulator
1.8V
Regulator
Supply
V
DD
V
DDIO,
V
DDA
V
IH
V
IL
Fall Time
Input Signal
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
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