參數(shù)資料
型號(hào): DSP56858VF120
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 43/64頁(yè)
文件大?。?/td> 956K
代理商: DSP56858VF120
Quad Timer Timing
56858 Technical Data, Rev. 6
Freescale Semiconductor
43
4.10 Quad Timer Timing
Figure 4-28 Timer Timing
4.11 Enhanced Synchronous Serial Interface (ESSI) Timing
Table 4-10 Quad Timer Timing
1, 2
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
50pF, f
op
= 120MHz
1.
In the formulas listed, T = clock cycle. For f
op
= 120MHz operation and fipb = 60MHz, T = 8.33ns.
Parameters listed are guaranteed by design.
2.
Characteristic
Symbol
Min
Max
Unit
Timer input period
P
IN
2T + 3
ns
Timer input high/low period
P
INHL
1T + 3
ns
Timer output period
P
OUT
2T - 3
ns
Timer output high/low period
P
OUTHL
1T - 3
ns
Table 4-11 ESSI Master Mode
1
Switching Characteristics
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
50pF, f
op
= 120MHz
Parameter
Symbol
Min
Typ
Max
Units
SCK frequency
fs
15
2
MHz
SCK period
3
t
SCKW
66.7
ns
SCK high time
t
SCKH
33.4
4
ns
SCK low time
t
SCKL
33.4
4
ns
Output clock rise/fall time
4
ns
Delay from SCK high to SC2 (bl) high - Master
5
t
TFSBHM
-1.0
1.0
ns
Timer Inputs
Timer Outputs
P
INHL
P
INHL
P
IN
P
OUTHL
P
OUTHL
P
OUT
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