參數(shù)資料
型號(hào): DSP56858VF120
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁數(shù): 44/64頁
文件大?。?/td> 956K
代理商: DSP56858VF120
56858 Technical Data, Rev. 6
44
Freescale Semiconductor
Delay from SCK high to SC2 (wl) high - Master
5
t
TFSWHM
-1.0
1.0
ns
Delay from SC0 high to SC1 (bl) high - Master
5
t
RFSBHM
-1.0
1.0
ns
Delay from SC0 high to SC1 (wl) high - Master
5
t
RFSWHM
-1.0
1.0
ns
Delay from SCK high to SC2 (bl) low - Master
5
t
TFSBLM
-1.0
1.0
ns
Delay from SCK high to SC2 (wl) low - Master
5
t
TFSWLM
-1.0
1.0
ns
Delay from SC0 high to SC1 (bl) low - Master
5
t
RFSBLM
-1.0
1.0
ns
Delay from SC0 high to SC1 (wl) low - Master
5
t
RFSWLM
-1.0
1.0
ns
SCK high to STD enable from high impedance - Master
t
TXEM
-0.1
2
ns
SCK high to STD valid - Master
t
TXVM
-0.1
2
ns
SCK high to STD not valid - Master
t
TXNVM
-0.1
ns
SCK high to STD high impedance - Master
t
TXHIM
-4
0
ns
SRD Setup time before SC0 low - Master
t
SM
4
ns
SRD Hold time after SC0 low - Master
t
HM
4
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRD Setup time before SCK low - Master
t
TSM
4
ns
SRD Hold time after SCK low - Master
t
THM
4
ns
1.
Master mode is internally generated clocks and frame syncs
2.
Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.
3.
All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4.
50 percent duty cycle
5.
bl = bit length; wl = word length
Table 4-11 ESSI Master Mode
1
Switching Characteristics (Continued)
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0 V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
=
3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
50pF, f
op
= 120MHz
Parameter
Symbol
Min
Typ
Max
Units
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