參數(shù)資料
型號(hào): DSP56858VF120
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 4/64頁(yè)
文件大小: 956K
代理商: DSP56858VF120
56858 Technical Data, Rev. 6
4
Freescale Semiconductor
Part 1 Overview
1.1 56858 Features
1.1.1
Digital Signal Processing Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses and one (1) external address bus
Four (4) internal data buses and one (1) external data bus
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C-Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
On-Chip Memory
— 40K
×
16-bit Program RAM
— 24K
×
16-bit Data RAM
— 1K
×
16-bit Boot ROM
Off-Chip Memory Expansion (EMI)
— Access up to 2M words of program or 8M data memory (using chip selects)
— Chip Select Logic for glue-less interface to ROM and SRAM
1.1.3
56858 Peripheral Circuit Features
General Purpose 16-bit Quad Timer*
Two Serial Communication Interfaces (SCI)*
Serial Peripheral Interface (SPI) Port*
Two (2) Enhanced Synchronous Serial Interface (ESSI) modules*
Computer Operating Properly (COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
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