參數(shù)資料
型號: DSP56F803BU80E
廠商: Freescale Semiconductor
文件頁數(shù): 16/52頁
文件大?。?/td> 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
特色產品: DSP56F803 Digital Signal Controller
標準包裝: 90
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 71KB(35.5K x 16)
程序存儲器類型: 閃存
RAM 容量: 2.5K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
Flash Memory Characteristics
56F803 Technical Data, Rev. 16
Freescale Semiconductor
23
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 3-3 Signal States
3.4 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
Mode
XE1
1.
X address enable, all rows are disabled when XE = 0
YE2
2.
Y address enable, YMUX is disabled when YE = 0
SE3
3.
Sense amplifier enable
OE4
4.
Output enable, tri-state Flash data out bus when OE = 0
PROG5
ERASE6
MAS17
NVSTR8
Standby
L
Read
H
HHH
L
Word Program
H
L
H
LLH
Page Erase
H
L
H
L
H
Mass Erase
H
L
H
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
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