參數(shù)資料
型號(hào)： DSP56F803BU80E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 3/52頁(yè)
文件大小： 0K
描述： IC DSP 80MHZ 64KB FLASH 100LQFP
特色產(chǎn)品： DSP56F803 Digital Signal Controller
標(biāo)準(zhǔn)包裝： 90
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 16
程序存儲(chǔ)器容量： 71KB（35.5K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.5K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤(pán)
Clock and Phase Locked Loop Signals
56F803 Technical Data, Rev. 16
Freescale Semiconductor
11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
EXTAL
Input
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
1
XTAL
Input/
Output
Chip-driven
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.5.3.
1
CLKO
Output
Chip-driven
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select Register
(CLKOSR), the user can select between outputting a version of the
signal applied to XTAL and a version of the device’s master clock at the
output of the PLL. The clock frequency on this pin can also be disabled
by programming the CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5
Output
Tri-stated
Address Bus—A0–A5 specify the address for external Program or Data
memory accesses.
2
A6–A7
GPIOE2–
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus—A6–A7 specify the address for external Program or Data
memory accesses.
Port E GPIO—These two pins are General Purpose I/O (GPIO) pins that
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
GPIOA0–
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight pins are General Purpose I/O (GPIO) pins
that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F803BU80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
DSP56F803BU80E 制造商:Freescale Semiconductor 功能描述:DSP LQFP100 3.6V
DSP56F803E 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
DSP56F803EVM 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 Evaluation Kit For DSP56F803 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
DSP56F803EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F803 Evaluation Module Hardware User＇s Manual
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