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參數(shù)資料
| 型號(hào)： | DSP56F803BU80E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 100LQFP |
| 特色產(chǎn)品： | DSP56F803 Digital Signal Controller |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | 56F8xx |
| 核心處理器： | 56800 |
| 芯體尺寸： | 16-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲(chǔ)器容量： | 71KB（35.5K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2.5K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-LQFP |
| 包裝： | 托盤 |
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor
33
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
15T
—
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
—
ns
IRQA Width Assertion to Recover from Stop State4
tIW
2T
—
ns
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
275,000T
12T
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
275,000T
12T
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
275,000T
12T
ns
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)1, 5
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
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| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
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