參數(shù)資料
型號: DSP56F827
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Hybrid Controller(16位混合控制器)
中文描述: 16位混合控制器(16位混合控制器)
文件頁數(shù): 28/52頁
文件大?。?/td> 1175K
代理商: DSP56F827
28
56F827 Technical Data
Figure 14. External Clock Timing
3.6.4
Phase Locked Loop Timing
Table 11. External Clock Operation Timing Requirements
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
1
1.
2.
3.
4.
See
Figure 13
for details on using the recommended connection of an external clock driver.
When using Time-of-Day (TOD), maximum external frequency is 6MHz.
The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
Parameters listed are guaranteed by design.
f
osc
0
4
80
2
MHz
Clock Pulse Width
3,
4
t
PW
6.25
ns
Table 12. PLL Timing
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Typ
Max
Unit
1
1.
correctly. The PLL is optimized for 4MHz input crystal.
2.
ZCLK may not exceed 80MHz. For additional information on ZCLK and
f
out
/2,
please refer to the OCCS chapter
in the User Manual. ZCLK = f
op
3.
This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
f
osc
2
4
6
MHz
PLL output frequency
2
f
out
/2
40
110
MHz
PLL stabilization time
3
-40
o
to +85
o
C
t
plls
1
10
ms
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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