參數(shù)資料
型號： DSP56F827FG80E
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號控制器
文件頁數(shù)： 28/60頁
文件大?。?/td> 811K
代理商： DSP56F827FG80E
56F827 Technical Data, Rev. 12
28
Freescale Semiconductor
Table 3-7 Flash Timing Parameters
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
Characteristic
Symbol
Min
Typ
Max
Unit
Figure
Program time
T
prog*
20
–
–
us
Figure 3-6
Erase time
T
erase*
20
–
–
ms
Figure 3-7
Mass erase time
T
me*
100
–
–
ms
Figure 3-8
Endurance
1
1.
One cycle is equal to an erase program and read.
E
CYC
10,000
20,000
–
cycles
Data Retention
1
D
RET
10
30
–
years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
T
nvs*
–
5
–
us
Figure 3-6
,
Figure 3-7
,
Figure 3-8
NVSTR hold time
T
nvh*
–
5
–
us
Figure 3-6
,
Figure 3-7
NVSTR hold time (mass erase)
T
nvh1*
–
100
–
us
Figure 3-8
NVSTR to program set up time
T
pgs*
–
10
–
us
Figure 3-6
,
Recovery time
T
rcv*
–
1
–
us
Figure 3-6
,
Figure 3-7
,
Figure 3-8
Cumulative program
HV period
2
2.
programmed twice before next erase.
Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
T
hv
–
3
–
ms
Figure 3-6
,
Program hold time
3
3.
Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
T
pgh
–
–
–
Figure 3-6
,
Address/data set up time
3
T
ads
–
–
–
Figure 3-6
,
Address/data hold time
3
T
adh
–
–
–
Figure 3-6
,
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