參數(shù)資料
型號(hào)： DSP56F827FG80E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 36/60頁(yè)
文件大?。?/td> 811K
代理商： DSP56F827FG80E
56F827 Technical Data, Rev. 12
36
Freescale Semiconductor
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 5
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—
21
ns
Figure 3-14
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
t
RA
275,000T
128T
—
—
ns
ns
Figure 3-14
RESET Deassertion to First External Address Output
t
RDA
33T
34T
ns
Figure 3-14
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
—
ns
Figure 3-15
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
t
IDM
15T
—
ns
Figure 3-16
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
16T
—
ns
Figure 3-16
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
3
3.
the minimum required so that the IRQA interrupt is accepted.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
t
IRI
13T
—
ns
Figure 3-17
IRQA Width Assertion to Recover from Stop State
4
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
t
IW
2T
—
ns
Figure 3-18
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
—
—
275,000T
12T
ns
ns
Figure 3-18
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
—
—
275,000T
12T
ns
ns
Figure 3-19
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
—
—
275,000T
12T
ns
ns
Figure 3-19
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