參數(shù)資料
型號(hào): DSP56F827FG80E
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁數(shù): 34/60頁
文件大?。?/td> 811K
代理商: DSP56F827FG80E
56F827 Technical Data, Rev. 12
34
Freescale Semiconductor
Input Data Hold to RD Deasserted
t
DRD
0
ns
RD Assertion Width
Wait states = 0
Wait states > 0
t
RD
19
(T*WS) + 19
ns
ns
Address Valid to Output Data Valid
Wait states = 0
Wait states > 0
t
AD
1
(T*WS) + 1
ns
ns
Address Valid to RD Asserted
t
ARDA
-4.4
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
t
RDD
2.4
(T*WS) + 2.4
ns
ns
WR Deasserted to RD Asserted
t
WRRD
6.8
ns
RD Deasserted to RD Asserted
t
RDRD
0
ns
WR Deasserted to WR Asserted
t
WRWR
14.1
ns
RD Deasserted to WR Asserted
t
RDWR
12.8
ns
1.
T = Clock Period. For 80MHz operation, T = 12.5ns.
Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-10 External Bus Asynchronous Timing
1, 2
(Continued)
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
50pF, f
op
= 80MHz
Characteristic
Symbol
Min
Max
Unit
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