參數(shù)資料
型號(hào)： DSP56F827FG80E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 44/60頁(yè)
文件大?。?/td> 811K
代理商： DSP56F827FG80E
56F827 Technical Data, Rev. 12
44
Freescale Semiconductor
Delay from STCK high to STFS (wl) low - Master
5
t
TFSWLM
-1.0
—
-0.1
ns
Delay from SRCK high to SRFS (bl) low - Master
5
t
RFSBLM
-0.1
—
0
ns
Delay from SRCK high to SRFS (wl) low - Master
5
t
RFSWLM
-0.1
—
0
ns
STCK high to STXD enable from high impedance - Master
t
TXEM
20
—
22
ns
STCK high to STXD valid - Master
t
TXVM
24
—
26
ns
STCK high to STXD not valid - Master
t
TXNVM
0.1
—
0.2
ns
STCK high to STXD high impedance - Master
t
TXHIM
24
—
25.5
ns
SRXD Setup time before SRCK low - Master
t
SM
4
—
—
ns
SRXD Hold time after SRCK low - Master
t
HM
4
—
—
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master
t
TSM
4
—
—
—
SRXD Hold time after STCK low - Master
t
THM
4
—
—
—
1.
Master mode is internally generated clocks and frame syncs
2.
Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3.
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
4.
50% duty cycle
5.
bl = bit length; wl = word length
Table 3-14 SSI Master Mode
1
Switching Characteristics
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
< 50pF, f
op
= 80MHz
Parameter
Symbol
Min
Typ
Max
Units
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