參數(shù)資料
型號(hào): EBJ41UF8BAS0-GN-F
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 1G X 64 DDR DRAM MODULE, ZMA204
封裝: HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204
文件頁數(shù): 18/21頁
文件大?。?/td> 204K
代理商: EBJ41UF8BAS0-GN-F
EBJ41UF8BAS0
Preliminary Data Sheet E1545E20 (Ver. 2.0)
6
Serial PD Matrix
Byte No. Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
value
Comments
0
Number of serial PD bytes written/SPD
device size/CRC coverage
-GN
0
00H
TBD
-DJ, -AE
1
0
1
0
1
0
92H
176/256/0-116
1
SPD revision
0
1
0
10H
Revision 1.0
2
Key byte/DRAM device type
0
1
0
1
0BH
DDR3 SDRAM
3
Key byte/module type
0
1
03H
SO-DIMM
4
SDRAM density and banks
0
1
03H
2G bits, 8 banks
5
SDRAM addressing
0
1
0
1
19H
15 rows, 10 columns
6
Module nominal voltage, VDD
0
00H
1.5V
7
Module organization
0
1
0
1
09H
2 ranks/
×8 bits
8
Module memory bus width
0
1
03H
64 bits/non-ECC
9
Fine timebase (FTB) dividend/divisor
0
1
0
1
0
1
0
52H
5/2
10
Medium timebase (MTB) dividend
0
1
01H
1
11
Medium timebase (MTB) divisor
0
1
0
08H
8
12
SDRAM minimum cycle time
(tCK (min.))
-GN
0
00H
TBD
-DJ
0
1
0
0CH
1.5ns
-AE
0
1
0FH
1.875ns
13
Reserved
0
00H
14
SDRAM /CAS latencies supported, LSB
-GN
0
00H
TBD
- DJ
0
1
0
3CH
CL = 6, 7, 8, 9
-AE
0
1
0
1CH
CL = 6, 7, 8
15
SDRAM /CAS latencies supported, MSB
0
00H
16
SDRAM minimum /CAS latencies time
(tAA (min.))
0
1
0
1
0
1
69H
13.125ns
17
SDRAM write recovery time (tWR (min))
0
1
0
78H
15ns
18
SDRAM minimum /RAS to /CAS delay
(tRCD)
0
1
0
1
0
1
69H
13.125ns
19
SDRAM minimum row active to row active
delay (tRRD)
-GN
0
00H
TBD
-DJ
0
1
0
30H
6ns
-AE
0
1
0
3CH
7.5ns
20
SDRAM minimum row precharge time
(tRP)
0
1
0
1
0
1
69H
13.125ns
21
SDRAM upper nibbles for tRAS and tRC
0
1
0
1
11H
22
SDRAM minimum active to precharge time
(tRAS), LSB
-GN
0
00H
TBD
-DJ
0
1
0
20H
36ns
-AE
0
1
0
1
0
2CH
37.5ns
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