參數(shù)資料
型號: EBJ41UF8BAS0-GN-F
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 1G X 64 DDR DRAM MODULE, ZMA204
封裝: HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204
文件頁數(shù): 2/21頁
文件大?。?/td> 204K
代理商: EBJ41UF8BAS0-GN-F
EBJ41UF8BAS0
Preliminary Data Sheet E1545E20 (Ver. 2.0)
10
Byte No. Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
value
Comments
202
SDRAM minimum row active to row active
delay (tRRD)
0
00H
TBD
203
Upper nibble for tFAW
0
00H
TBD
204
Minimum four activate window delay time
(tFAW)
0
00H
TBD
205
SDRAM minimum internal write to read
command delay (tWTR)
0
00H
TBD
206
Write to read & read to write command
turn-around time pull-in
0
00H
TBD
207
Back to back command turn-around time
pull-in
0
00H
TBD
208
System address/ command rate (1N or 2N
mode)
0
00H
TBD
209
Auto self-refresh performance (sub 1x
refresh and IDD6 impacts)
0
00H
TBD
210 to
218
Reserved
0
00H
219
Vendor personality byte
0
00H
[For Profile 2]
Byte No. Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex
value
Comments
220
Module VDD voltage level (extreme
settings)
0
00H
TBD
221
SDRAM minimum cycle time (tCK (min))
0
00H
TBD
222
Minimum CAS latency time (tAA (min))
0
00H
TBD
223
SDRAM /CAS latencies supported, LSB
(CL MASK)
0
00H
TBD
224
SDRAM /CAS latencies supported, MSB
(CL MASK)
0
00H
225
Minimum CAS write latency time
(tCWL (min))
0
00H
TBD
226
SDRAM minimum row precharge time
(tRP)
0
00H
TBD
227
SDRAM minimum /RAS to /CAS delay
(tRCD)
0
00H
TBD
228
SDRAM write recovery time (tWR (min))
0
00H
TBD
229
SDRAM upper nibbles for tRAS and tRC
0
00H
TBD
230
SDRAM minimum active to precharge time
(tRAS), LSB
0
00H
TBD
231
SDRAM minimum active to active /auto-
refresh time (tRC), LSB
0
00H
TBD
232
Maximum average periodic refresh interval
(tREFI), LSB
0
00H
TBD
233
Maximum average periodic refresh interval
(tREFI), MSB
0
00H
TBD
234
SDRAM minimum refresh recovery time
delay (tRFC), LSB
0
00H
TBD
235
SDRAM minimum refresh recovery time
delay (tRFC), MSB
0
00H
TBD
236
SDRAM minimum internal read to
precharge command delay (tRTP)
0
00H
TBD
237
SDRAM minimum row active to row active
delay (tRRD)
0
00H
TBD
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