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參數(shù)資料
| 型號： | EBJ41UF8BAS0-GN-F |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 1G X 64 DDR DRAM MODULE, ZMA204 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, SODIMM-204 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 204K |
| 代理商： | EBJ41UF8BAS0-GN-F |
EBJ41UF8BAS0
Preliminary Data Sheet E1545E20 (Ver. 2.0)
17
Pin Functions
CK, /CK (input pin)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with
multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
A0 to A14 (input pins)
Provided the row address for active commands and the column address for read/write commands to select one
location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see
below) The address inputs also provide the op-code during mode register set commands.
[Address Pins Table]
Address (A0 to A14)
Row address (RA)
Column address (CA)
Notes
AX0 to AX14
AY0 to AY9
A10(AP) (input pin)
A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the
accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA).
A12 (/BC) (input pin)
A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed.
(A12 = high: no burst chop, A12 = low: burst chopped.)
BA0 to BA2 (input pins)
BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and
BA1 also determine if a mode register is to be accessed during a MRS cycle.
[Bank Select Signal Table]
BA0
BA1
BA2
Bank 0
L
Bank 1
H
L
Bank 2
L
H
L
Bank 3
H
L
Bank 4
L
H
Bank 5
H
L
H
Bank 6
L
H
Bank 7
H
Remark:
H: VIH. L: VIL.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EC11.0001.001 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.201 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.301 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0001.401 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
| EC11.0021.001 | Power Entry Module; IEC; Voltage Rating: 250V; Current Rating: 20A; Terminal Type: Quick Connect Tabs; Appliance inlet with line switch; 2-pole; single elements are already wired |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EBJ41UF8BCF0 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Unbuffered DDR3 SDRAM DIMM |
| EBJ41UF8BCF0-DJ-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Unbuffered DDR3 SDRAM DIMM |
| EBJ41UF8BCF0-GN-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB Unbuffered DDR3 SDRAM DIMM |
| EBJ41UF8BCS0 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB DDR3 SDRAM SO-DIMM |
| EBJ41UF8BCS0-DJ-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:4GB DDR3 SDRAM SO-DIMM |
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