- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384279 > EDE2104ABSE (Elpida Memory, Inc.) 2G bits DDR2 SDRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | EDE2104ABSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 2G bits DDR2 SDRAM |
| 中文描述： | 第二代位DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 18/81頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EDE2104ABSE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
EDE2104ABSE, EDE2108ABSE
Preliminary Data Sheet E1196E10 (Ver. 1.0)
18
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not
an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing
tQH.
The value to be used for tQH calculation is determined by the following equation;
tHP = min ( tCH(abs), tCL(abs) ),
where,
tCH(abs) is the minimum of the actual instantaneous clock high time;
tCL(abs) is the minimum of the actual instantaneous clock low time;
7. tQHS accounts for:
a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the
input is transferred to the output; and
b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are independent of each other, due to data pin skew, output pattern effects,
and p-channel to n-channel variation of the output drivers.
8. tQH = tHP – tQHS, where:
tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification
value under the max column.
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye
will be.}
Examples:
a. If the system provides tHP of 1315ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975ps
(min.)
b. If the system provides tHP of 1420ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080ps
(min.)
9. RU stands for round up. WR refers to the tWR parameter stored in the MRS.
10. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. =
272ps and
tERR(6-10per) max. = +293ps, then tDQSCK min.(derated) = tDQSCK min.
tERR(6-10per) max. =
400ps
293ps =
693ps and tDQSCK max.(derated) = tDQSCK max.
tERR(6-10per) min. = 400ps +
272ps = +672ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ) min.(derated) =
900ps
293ps =
1193ps and tLZ(DQ) max.(derated)= 450ps + 272ps = +722ps.
11. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per) min. =
72ps and
tJIT(per) max. = +93ps, then tRPRE min.(derated) = tRPRE min. + tJIT(per) min. = 0.9
×
tCK(avg)
72ps
= +2178ps and tRPRE max.(derated) = tRPRE max. + tJIT(per) max. = 1.1
×
tCK(avg) + 93ps = +2843ps.
12. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty) min. =
72ps and
tJIT(duty) max. = +93ps, then tRPST min.(derated) = tRPST min. + tJIT(duty) min. = 0.4
×
tCK(avg)
72ps = +928ps and tRPST max.(derated) = tRPST max. + tJIT(duty) max. = 0.6
×
tCK(avg) + 93ps =
+1592ps.
13. Refer to the Clock Jitter table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE2104ABSE-5C-E | 2G bits DDR2 SDRAM |
| EDE2104ABSE-6E-E | 2G bits DDR2 SDRAM |
| EDE2104ABSE-8G-E | 2G bits DDR2 SDRAM |
| EDE2108ABSE | 2G bits DDR2 SDRAM |
| EDE2108ABSE-5C-E | 2G bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE2104ABSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2104ABSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2104ABSE-8G-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2108ABSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2108ABSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。