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參數(shù)資料
| 型號(hào)： | EDE2104ABSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 2G bits DDR2 SDRAM |
| 中文描述： | 第二代位DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 30/81頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EDE2104ABSE |
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EDE2104ABSE, EDE2108ABSE
Preliminary Data Sheet E1196E10 (Ver. 1.0)
30
Pin Function
CK, /CK (input pins)
CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
/CS (input pin)
All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with
multiple ranks. /CS is considered part of the command code.
/RAS, /CAS, /WE (input pins)
/RAS, /CAS and /WE (along with /CS) define the command being entered.
A0 to A14 (input pins)
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write
commands to select one location out of the memory array in the respective bank. The address inputs also provide
the op-code during mode register set commands.
[Address Pins Table]
Address (A0 to A14)
Part number
Row address
Column address
Note
EDE2104ABSE
AX0 to AX14
AY0 to AY9, AY11
EDE2108ABSE
AX0 to AX14
AY0 to AY9
A10 (AP) (input pin)
A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low)
or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by BA0, BA1 and BA2.
BA0, BA1, BA2 (input pins)
BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and
BA1 also determine if the mode register or extended mode register is to be accessed during a MRS or EMRS (1),
EMRS (2) cycle.
[Bank Select Signal Table]
BA0
BA1
BA2
Bank 0
L
L
L
Bank 1
H
L
L
Bank 2
L
H
L
Bank 3
H
H
L
Bank 4
L
L
H
Bank 5
H
L
H
Bank 6
L
H
H
Bank 7
H
H
H
Remark: H: VIH. L: VIL.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE2104ABSE-5C-E | 2G bits DDR2 SDRAM |
| EDE2104ABSE-6E-E | 2G bits DDR2 SDRAM |
| EDE2104ABSE-8G-E | 2G bits DDR2 SDRAM |
| EDE2108ABSE | 2G bits DDR2 SDRAM |
| EDE2108ABSE-5C-E | 2G bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE2104ABSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2104ABSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2104ABSE-8G-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2108ABSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
| EDE2108ABSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM |
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