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參數(shù)資料
| 型號： | EDE5108AHSE-6E-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 64M X 8 DDR DRAM, 0.45 ns, PBGA60 |
| 封裝： | ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 10/64頁 |
| 文件大?。?/td> | 871K |
| 代理商： | EDE5108AHSE-6E-E |
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Datasheet
DD2.x
PowerPC 750CL Microprocessor
Preliminary
Electrical and Thermal Characteristics
Page 18 of 65
750cl_ds_body.fm.2.4
May 29, 2007
3.3 Clock Specifications
Table 3-6 provides the clock AC timing specifications as defined in Figure 3-1.
Table 3-6. Clock AC Timing Specifications
See Table 3-2 on page 15 for recommended operating conditions.1, 3, 5
Figure 3-1
Timing
Reference
Characteristic
Value
Unit
Notes
Min.
Max.
Processor frequency
400
1000
MHz
SYSCLK frequency
50
240
MHz
Internal PLL relock time
—
100
μs4
Internal PLL reset time
10
—
μs5
Single-Ended SYSCLK Specifications
2, 3
SYSCLK slew rate, single-ended
2.50
10.0
V/ns
4
SYSCLK duty cycle measured at Vm-SYsClk, single-ended
25
75
%
Jitter, over any 10 consecutive cycles
—
160
ps
Jitter, over any 50 consecutive cycles
—
240
ps
Jitter, over any 100 consecutive cycles
—
380
ps
Jitter, over any 1000 consecutive cycles
—
640
ps
Differential SYSCLK and SYSCLK Specifications
2, 3
SYSCLK and SYSCLK slew rate, differential
1.50
3.0
V/ns
4
SYSCLK and SYSCLK duty cycle measured at Vm-SYsClk, differential
40
60
%
Jitter, cycle-to-cycle
—
200
ps (P - P)
Jitter, long term
—
2.5
%
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies.
Refer to the PLL_CFG[0:4] signal description in Table 5-1, 750CL Microprocessor PLL Configuration, on page 37 for valid
PLL_CFG[0:4] settings.
2. The slew rate for the single-ended SYSCLK inputs is measured from 0.4 to 0.75 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time
required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. Also note that hard reset
(HRESET) must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
5. Midpoint voltage (VM) for SYSCLK and SYSCLK is VDD/2. The SYSCLK and SYSCLK input voltage range depends on OVDD, but
VM is a function of VDD.
6. This is the maximum deviation from nominal in the timing of the rising edge of SYSCLK over the indicated number of cycles.
7. The slew rate for SYSCLK and SYSCLK is measured between the 10% and 90% points of each clock input.
8. Long term jitter is given as a percentage of the input clock period occurring over a 10
μs interval.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE5108AHSE-8E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AHSE-8G-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJBG | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJBG-1J | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
| EDE5108AJBG-1J-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits DDR2 SDRAM |
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