參數(shù)資料
型號: EDE5108AHSE-6E-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 64M X 8 DDR DRAM, 0.45 ns, PBGA60
封裝: ROHS COMPLIANT, FBGA-60
文件頁數(shù): 3/64頁
文件大小: 871K
代理商: EDE5108AHSE-6E-E
Datasheet
DD2.x
Preliminary
PowerPC 750CL Microprocessor
750cl_ds_body.fm.2.4
May 29, 2007
General Information
Page 11 of 65
64-byte cache line organized as two 32-byte sectors
L2 frequency at core speed
Selectable 32-byte, 64-byte, or 128-byte L2 cache loads
Error correction code (ECC) protection on cache array
Bus interface
Compatible with the 60x processor interface
Has a 32-bit address bus
Has a 64-bit data bus (also supports 32-bit data bus mode)
Supports bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,
8x, 8.5x, 9x, 9.5x, and 10x
Bus transaction pipeline depth of 2, 3, or 4 transactions (selectable)
Testability
Level sensitive scan design (LSSD)
JTAG interface
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