參數(shù)資料
型號: EFM32TG822F32
廠商: Energy Micro
文件頁數(shù): 20/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Tiny Gecko
標準包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標準包裝
其它名稱: 914-1031-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
116
www.energymicro.com
Bits
Name
Function
0 = MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value
of the ENABLE bit
1 = the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
[0]
ENABLE
Enables the MPU:
0 = MPU disabled
1 = MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
For privileged accesses, the default memory map is as described in Section 2.2 (p. 14) . Any access
by privileged software that does not address an enabled memory region behaves as defined by the
default memory map.
Any access by unprivileged software that does not address an enabled memory region causes a
memory management fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of
the ENABLE bit.
When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system
to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions
are enabled, then only privileged software can operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory
attributes as if the MPU is not implemented, see Table 2.11 (p. 16) . The default memory map applies
to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted.
Other areas are accessible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for
an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI
exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit to 1 enables the MPU when
operating with these two priorities.
4.5.3 MPU Region Number Register
The RNR selects which memory region is referenced by the RBAR and RASR registers. See the register
summary in Table 4.38 (p. 114) for its attributes. The bit assignments are:
Reserved
31
8 7
0
REGION
Table 4.41. RNR bit assignments
Bits
Name
Function
[31:8]
-
Reserved.
[7:0]
REGION
Indicates the MPU region referenced by the RBAR and RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
Normally, you write the required region number to this register before accessing the RBAR or RASR.
However you can change the region number by writing to the RBAR with the VALID bit set to 1, see
Section 4.5.4 (p. 117) . This write updates the value of the REGION field.
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