參數(shù)資料
型號(hào): EFM32TG822F32
廠商: Energy Micro
文件頁數(shù): 70/136頁
文件大小: 0K
描述: IC MCU 32BIT 32KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1031-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
39
www.energymicro.com
#constant
where constant can be:
any constant that can be produced by shifting an 8#bit value left by any number of bits within a 32#bit
word
any constant of the form 0x00XY00XY
any constant of the form 0xXY00XY00
any constant of the form 0xXYXYXYXY.
Note
In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are
described in the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ
or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and
can be produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2
is any other constant.
3.3.3.1.1 Instruction substitution
Your assembler might be able to produce an equivalent instruction in cases where you specify a constant
that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE
as the equivalent instruction CMN Rd, #0x2.
3.3.3.2 Register with optional shift
You specify an Operand2 register in the form:
Rm {, shift}
where:
Rm
is the register holding the data for the second operand.
shift
is an optional shift to be applied to Rm. It can be one of:
ASR #n
arithmetic shift right n bits, 1 # n # 32.
LSL #n
logical shift left n bits, 1 # n # 31.
LSR #n
logical shift right n bits, 1 # n # 32.
ROR #n
rotate right n bits, 1 # n # 31.
RRX
rotate right one bit, with extend.
-
if omitted, no shift occurs, equivalent to LSL #0.
If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.
If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift
also updates the carry flag when used with certain instructions. For information on the shift operations
and how they affect the carry flag, see Section 3.3.4 (p. 39)
3.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift
length. Register shift can be performed:
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