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參數(shù)資料
| 型號： | EM78P451S |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | Quad, Serial, 8-Bit DACs with Rail-to-Rail Outputs |
| 中文描述： | 8位微控制器的OTP ROM的 |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 421K |
| 代理商： | EM78P451S |
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EM78P451S
8-Bit Microcontroller with OTP ROM
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
13
Bit 4 (SLPC)
This bit is set by hardware at the falling edge of wake-up signal and is
cleared in software. SLPC is used to control the oscillator operation. The
oscillator is disabled (oscillator is stopped, and the controller enters the
SLEEP2 mode) on the high-to-low transition and is enabled (the controller
is awakened from SLEEP2 mode) on low-to-high transition. In order to
ensure the stable output of the oscillator, once the oscillator is enabled
again, there is a delay for approximately 18 ms (oscillator start-up timer
(OST)) before the next program instruction is executed. The OST is
always activated by wake-up from sleep mode whether the Code Option bit
ENWDT is "0" or not. After waking up, the WDT is enabled if Code Option
ENWDT is "1". The block diagram of SLEEP2 mode and wake-up caused
by input triggered is depicted in Fig. 5. The SLPC bit can be read and
written.
Bit 3 (ROC)
ROC is used for the R-option. Setting ROC to "1" will enable the status of
R-option pins (P80, P81) to be read by the controller. Clearing ROC will
disable the R-option function. Otherwise, the R-option function is
introduced. Users must connect the P81 pin or/and P80 pin to VSS by a
560K
external resistor (Rex). If Rex is connected/disconnected with
VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The
ROC bit can be read and written.
Bit 0 (/WUE)
Control bit used to enable the wake-up function of P60~P67, P74~P75,
and P90~P91.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
4.2.7
IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
-
-
-
-
TM1IE
SPIIE
EXIE
TCIE
Bits 4~7
Not used.
Individual interrupt is enabled by setting its associated control bit in IOCF to "1".
The IOCF Register could be read and written.
Bit 3 (TM1IE)
TM1IE interrupt enable bit.
0: disable TM1IE interrupt
1: enable TM1IE interrupt
Bit 2 (SPIIE)
SPI interrupt enable bit.
0: disable SPI interrupt
1: enable SPI interrupt
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