參數(shù)資料
型號： EM78P451S
廠商： ELAN Microelctronics Corp .
英文描述： Quad, Serial, 8-Bit DACs with Rail-to-Rail Outputs
中文描述： 8位微控制器的OTP ROM的
文件頁數(shù)： 36/54頁
文件大?。?/td> 421K
代理商： EM78P451S
EM78P451S
8-Bit Microcontroller with OTP ROM
32
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S POR voltage range is 1.2V~2.0V. Under customer application, when
power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power
can be switched ON again. This way, the EM78P451S will reset and work normally.
The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or
less). However, under most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problem.
The device is kept in a RESET condition for a period of approx. 18ms
2
(one oscillator
start-up timer period) after the reset is detected and Fig.16 is the block diagram of
reset. Once the RESET occurs, the following functions are performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "1".
When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
The Watchdog timer is enabled if Code Option bit ENWDT is "1".
The CONT register is set to all "1" except bit 6 (INT flag).
Bits 3,6 of IOCE register are cleared, bits 0,4~5 of IOCE register are set to "1".
Bits 0 of R3F and bits 0 of IOCF registers are cleared.
The sleep mode (power down) is achieved by executing the SLEP instruction (named
as SLEEP1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but
keeps on running. The controller is awakened by WDT timeout (if enabled), and it will
cause the controller to reset. The T and P flags of R3 are used to determine the source
of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78P451S has another sleep mode (caused
by clearing "SLPC" bit of IOCE register, designated as SLEEP2 MODE). In the
SLEEP2 MODE, the controller can be awakened by-
(a)
Any one of the wake-up pins is set to “0.” (refer to Fig.17). Upon waking, the
controller will continue to execute the program in-line. In this case, before entering
SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67, P74~P75,
and P90~P91)should be selected (e.g. input pin) and enabled (e.g. pull-high,
wake-up control). One caution should be noted is that after waking up, the WDT is
enabled if Code Option bit ENWDT is "1". The WDT operation (to be enabled or
disabled) should be appropriately controlled by software after waking up.
(b)
WDT time-out (if enabled). or external reset input on /RESET pin will trigger a
controller reset..
2
NOTE: Vdd = 5V, set up time period = 16.20ms ± 30%
Vdd = 3V, set up time period = 18.0ms ±30%
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