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參數(shù)資料
| 型號(hào)： | EM78P451S |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | Quad, Serial, 8-Bit DACs with Rail-to-Rail Outputs |
| 中文描述： | 8位微控制器的OTP ROM的 |
| 文件頁數(shù)： | 40/54頁 |
| 文件大小： | 421K |
| 代理商： | EM78P451S |
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EM78P451S
8-Bit Microcontroller with OTP ROM
36
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
ODE
WTE
SLP
C
ROC
-
-
/WU
E
0x0E
IOCE
Power-On
U
0
1
1
0
U
U
1
/RESET and WDT
Wake-Up from Pin
Change
U
0
1
1
0
U
U
1
U
P
1
1
P
U
U
P
Bit Name
-
-
-
-
T1IE
SPII
E
0
EXIE
TCIE
0x0F
IOCF
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
U
U
U
U
0
0
0
U
U
U
U
0
0
0
0
U
U
U
U
P
P
P
P
-
-
-
-
-
-
-
-
0x10~0x3E
GPR
Power-On
/RESET and WDT
Wake-Up from Pin
Change
U
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
**
To execute the next instruction after the ”SLPC” bit status of IOCE register being on
high-to-low transition.
X: NOTE
used. U: Unknown or don’t care. -: Not defined P: Previous value before reset.
t: Check Table 7
The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition,
2. Watchdog timer time-out.
The values of T and P, listed in Table 7 are used to check how the processor wakes up.
Table 8 shows the events that may affect the status of T and P.
Table 8 The Values of RST, T and P After RESET
Reset Type
T
P
Power on
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
1
0
0
0
P
1
P
0
P
P
*
P: Previous value before reset
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