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參數(shù)資料
| 型號： | EM78P451S |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | Quad, Serial, 8-Bit DACs with Rail-to-Rail Outputs |
| 中文描述： | 8位微控制器的OTP ROM的 |
| 文件頁數(shù)： | 41/54頁 |
| 文件大小： | 421K |
| 代理商： | EM78P451S |
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EM78P451S
8-Bit Microcontroller with OTP ROM
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
37
Table 9 The Status of RST, T and P Being Affected by Events
Event
T
P
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-Up on pin change during SLEEP2 mode
1
1
0
1
P
1
1
*
P
0
P
*
P: Previous value before reset
4.8 Interrupt
The EM78P451S has the following interrupts.
1. /TCC overflow interrupt
2. External interrupt (/INT)
3. Serial Peripheral Interface (SPI) transmission completed interrupt.
4. Timer1 comparator completed interrupt.
R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF
is the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (if enabled) is generated, will
cause the next instruction to be fetched from address 001H. Once in the interrupt
service routine the source of the interrupt can be determined by polling the flag bits in
the R3F register. The interrupt flag bit must be cleared by software before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask
bit or the execution of ENI instruction. Note that reading R3F will obtain the output of
logic AND of R3F and IOCF (refer to Fig. 17). The RETI instruction exits interrupt
routine and enables the global interrupt (execution of ENI instruction).
When an interrupt is generated by INT instruction (if enabled), it causes the next
instruction to be fetched from address 002H.
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