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參數(shù)資料
| 型號： | EMBEDDED INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded INTEL486 SX Processor(嵌入式INTEL486 SX處理器) |
| 中文描述： | 山西嵌入式英特爾486處理器（嵌入式英特爾486山西處理器） |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 532K |
| 代理商： | EMBEDDED INTEL486 SX |
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Embedded Intel486 SX Processor
16
BUS CYCLE DEFINITION
M/IO#
D/C#
W/R#
O
O
O
Memory/Input-Output
,
Data/Control
and
Write/Read
ines are the primary bus
definition signals. These signals are driven valid as the ADS# signal is asserted.
M/IO#
D/C#
W/R#
Bus Cycle Initiated
0
0
0
Interrupt Acknowledge
0
0
1
HALT/Special Cycle (see details below)
0
1
0
I/O Read
0
1
1
I/O Write
1
0
0
Code Read
1
0
1
Reserved
1
1
0
Memory Read
1
1
1
Memory Write
HALT/Special Cycle
Cycle Name
BE3# - BE0#
Shutdown
1110
HALT
1011
Stop Grant bus cycle
1011
Bus Lock
ndicates that the current bus cycle is locked. The embedded Intel486
SX processor does not allow a bus hold when LOCK# is asserted (address holds
are allowed). LOCK# goes active in the first clock of the first locked bus cycle and
goes inactive after the last clock of the last locked bus cycle. The last locked cycle
ends when Ready is returned. LOCK# is active LOW and not driven during bus
hold. Locked read cycles are not transformed into cache fill cycles when KEN# is
returned active.
Pseudo-Lock
indicates that the current bus transaction requires more than one
bus cycle to complete. For the embedded Intel486 SX processor, examples of
such operations are segment table descriptor reads (64 bits) and cache line fills
(128 bits).
The embedded Intel486 SX processor drives PLOCK# active until the addresses
for the last bus cycle of the transaction are driven, regardless of whether RDY# or
BRDY# have been returned.
PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be
sampled only in the clock in which Ready is returned. PLOCK# is active LOW and
is not driven during bus hold.
A4-A2
000
000
100
LOCK#
O
PLOCK#
O
BUS CONTROL
ADS#
O
Address Status
output indicates that a valid bus cycle definition and address are
available on the cycle definition lines and address bus. ADS# is driven active in the
same clock in which the addresses are driven. ADS# is active LOW and not driven
during bus hold.
Table 7.
Embedded Intel486 SX Processor Pin Descriptions
(Sheet 2 of 6)
Symbol
Type
Name and Function
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