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參數(shù)資料
| 型號(hào)： | EMBEDDED INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded INTEL486 SX Processor(嵌入式INTEL486 SX處理器) |
| 中文描述： | 山西嵌入式英特爾486處理器（嵌入式英特爾486山西處理器） |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 532K |
| 代理商： | EMBEDDED INTEL486 SX |
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Embedded Intel486 SX Processor
1
1.0
INTRODUCTION
The embedded Intel486 SX processor provides
high performance to 32-bit, embedded applications.
Designed for applications that do not need a floating-
point unit, the processor is ideal for embedded
designs running DOS
, Microsoft Windows
, OS/2
*
,
or UNIX
applications written for the Intel archi-
tecture. Projects can be completed quickly by
utilizing the wide range of software tools, utilities,
assemblers and compilers that are available for
desktop computer systems. Also, developers can
find advantages in using existing chip sets and
peripheral components in their embedded designs.
The embedded Intel486 SX processor is binary
compatible with the Intel386 and earlier Intel
processors. Compared with the Intel386 processor, it
provides faster execution of many commonly-used
instructions. It also provides the benefits of an
integrated, 8-Kbyte, write-through cache for code
and data. Its data bus can operate in burst mode
which
provides
up
to
transfers
for
cache-line
prefetches.
106-Mbyte-per-second
fills
and
instruction
Intel’s SL technology is incorporated in the
embedded Intel486 SX processor. Utilizing Intel’s
System Management Mode (SMM), it enables
designers to develop energy-efficient systems.
Two component packages are available. A 196-lead
Plastic Quad Flat Pack (PQFP) is available for 5-Volt
designs and a 208-lead Shrink Quad Flat Pack
(SQFP) is available for 3.3-Volt designs. Both
products operate at CLK frequencies up to 33 MHz.
1.1
Features
The embedded Intel486 SX processor offers these
features:
32-bit RISC-Technology Core
— The embedded
Intel486 SX processor performs a complete set of
arithmetic and logical operations on 8-, 16-, and
32-bit data types using a full-width ALU and eight
general purpose registers.
Single Cycle Execution
— Many instructions
execute in a single clock cycle.
Instruction Pipelining
— Overlapped instruction
fetching, decoding, address translation and
execution.
*
Other brands and names are the property of their
respective owners.
On-Chip Cache with Cache Consistency
Support
— An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
External Cache Control
— Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
On-Chip Memory Management Unit
— Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitudinous and virtual memory environment.
Both memory segmentation and paging are
supported.
Burst Cycles
— Burst transfers allow a new
double-word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache.
Write Buffers
— The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
Bus Backoff
— When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded Intel486 SX processor floats
its bus signals, then restarts the cycle when the
bus becomes available again.
Instruction Restart
— Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
Dynamic Bus Sizing
— External controllers can
dynamically alter the effective width of the data
bus. Bus widths of 8, 16, or 32 bits can be used.
Boundary Scan (JTAG)
— Boundary Scan
provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.
Intel’s SL technology provides these features:
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