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參數(shù)資料
| 型號： | EMBEDDED INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded INTEL486 SX Processor(嵌入式INTEL486 SX處理器) |
| 中文描述： | 山西嵌入式英特爾486處理器（嵌入式英特爾486山西處理器） |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 532K |
| 代理商： | EMBEDDED INTEL486 SX |
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Embedded Intel486 SX Processor
17
RDY#
I
Non-burst Ready
nput indicates that the current bus cycle is complete. RDY#
indicates that the external system has presented valid data on the data pins in
response to a read or that the external system has accepted data from the
embedded Intel486 SX processor in response to a write. RDY# is ignored when the
bus is idle and at the end of the first clock of the bus cycle.
RDY# is active during address hold. Data can be returned to the embedded
Intel486 SX processor while AHOLD is active.
RDY# is active LOW and is not provided with an internal pull-up resistor. RDY#
must satisfy setup and hold times t
16
and t
17
for proper chip operation.
BURST CONTROL
BRDY#
I
Burst Ready
nput performs the same function during a burst cycle that RDY#
performs during a non-burst cycle. BRDY# indicates that the external system has
presented valid data in response to a read or that the external system has
accepted data in response to a write. BRDY# is ignored when the bus is idle and at
the end of the first clock in a bus cycle.
BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data
presented on the data bus is strobed into the embedded Intel486 SX processor
when BRDY# is sampled active. If RDY# is returned simultaneously with BRDY#,
BRDY# is ignored and the burst cycle is prematurely aborted.
BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must
satisfy the setup and hold times t
16
and t
17
.
Burst Last
signal indicates that the next time BRDY# is returned, the burst bus
cycle is complete. BLAST# is active for both burst and non-burst bus cycles.
BLAST# is active LOW and is not driven during bus hold.
BLAST#
O
INTERRUPTS
RESET
I
Reset
input forces the embedded Intel486 SX processor to begin execution at a
known state. The processor cannot begin executing instructions until at least 1 ms
after V
, and CLK have reached their proper DC and AC specifications. The
RESET pin must remain active during this time to ensure proper processor
operation. However, for warm resets, RESET should remain active for at least 15
CLK periods. RESET is active HIGH. RESET is asynchronous but must meet
setup and hold times t
20
and t
21
for recognition in any specific clock.
Maskable Interrupt
ndicates that an external interrupt has been generated. When
the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated.
The embedded Intel486 SX processor generates two locked interrupt acknowledge
bus cycles in response to the INTR pin going active. INTR must remain active until
the interrupt acknowledges have been performed to ensure processor recognition
of the interrupt.
INTR is active HIGH and is not provided with an internal pull-down resistor. INTR is
asynchronous, but must meet setup and hold times t
20
and t
21
for recognition in
any specific clock.
Non-Maskable Interrupt
request signal indicates that an external non-maskable
interrupt has been generated. NMI is rising-edge sensitive and must be held LOW
for at least four CLK periods before this rising edge. NMI is not provided with an
internal pull-down resistor. NMI is asynchronous, but must meet setup and hold
times t
20
and t
21
for recognition in any specific clock.
INTR
I
NMI
I
Table 7.
Embedded Intel486 SX Processor Pin Descriptions
(Sheet 3 of 6)
Symbol
Type
Name and Function
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