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參數(shù)資料
| 型號： | EMBEDDED INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded INTEL486 SX Processor(嵌入式INTEL486 SX處理器) |
| 中文描述： | 山西嵌入式英特爾486處理器（嵌入式英特爾486山西處理器） |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 532K |
| 代理商： | EMBEDDED INTEL486 SX |
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Embedded Intel486 SX Processor
19
BOFF#
I
Backoff
nput forces the embedded Intel486 SX processor to float its bus in the
next clock. The processor floats all pins normally floated during bus hold but HLDA
is not asserted in response to BOFF#. BOFF# has higher priority than RDY# or
BRDY#; if both are returned in the same clock, BOFF# takes effect. The embedded
Intel486 SX processor remains in bus hold until BOFF# is negated. If a bus cycle is
in progress when BOFF# is asserted the cycle is restarted. BOFF# is active LOW
and must meet setup and hold times t
18
and t
19
for proper operation.
CACHE INVALIDATION
AHOLD
I
Address Hold
request allows another bus master access to the embedded
Intel486 SX processor’s address bus for a cache invalidation cycle. The processor
stops driving its address bus in the clock following AHOLD going active. Only the
address bus is floated during address hold, the remainder of the bus remains
active. AHOLD is active HIGH and is provided with a small internal pull-down
resistor. For proper operation, AHOLD must meet setup and hold times t
18
and t
19
.
External Address
- This signal indicates that a
valid
external address has been
driven onto the embedded Intel486 SX processor address pins. This address is
used to perform an internal cache invalidation cycle. EADS# is active LOW and is
provided with an internal pull-up resistor. EADS# must satisfy setup and hold times
t
12
and t
13
for proper operation.
EADS#
I
CACHE CONTROL
KEN#
I
Cache Enable
pin is used to determine whether the current cycle is cacheable.
When the embedded Intel486 SX processor generates a cycle that can be cached
and KEN# is active one clock before RDY# or BRDY# during the first transfer of the
cycle, the cycle becomes a cache line fill cycle. Returning KEN# active one clock
before RDY# during the last read in the cache line fill causes the line to be placed
in the on-chip cache. KEN# is active LOW and is provided with a small internal pull-
up resistor. KEN# must satisfy setup and hold times t
14
and t
15
for proper
operation.
Cache Flush
input forces the embedded Intel486 SX processor to flush its entire
internal cache. FLUSH# is active LOW and need only be asserted for one clock.
FLUSH# is asynchronous but setup and hold times t
20
and t
21
must be met for
recognition in any specific clock.
FLUSH#
I
PAGE CACHEABILITY
PWT
PCD
O
O
Page Write-Through
and
Page Cache Disable
pins reflect the state of the page
attribute bits, PWT and PCD, in the page table entry, page directory entry or
control register 3 (CR3) when paging is enabled. When paging is disabled, the
embedded Intel486 SX processor ignores the PCD and PWT bits and assumes
they are zero for the purpose of caching and driving PCD and PWT pins. PWT and
PCD have the same timing as the cycle definition pins (M/IO#, D/C#, and W/R#).
PWT and PCD are active HIGH and are not driven during bus hold. PCD is masked
by the cache disable bit (CD) in Control Register 0.
Table 7.
Embedded Intel486 SX Processor Pin Descriptions
(Sheet 5 of 6)
Symbol
Type
Name and Function
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